udasyncounter.vho

Up-down Asynchronous counter in Behavioral Model

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 5.1 Build 176 10/26/2005 SJ Web Edition"

-- DATE "10/10/2007 15:59:14"

-- 
-- Device: Altera EP1C6Q240C8 Package PQFP240
-- 

-- 
-- This VHDL file should be used for ModelSim (VHDL) only
-- 

LIBRARY IEEE, cyclone;
USE IEEE.std_logic_1164.all;
USE cyclone.cyclone_components.all;

ENTITY 	UDasyncounter IS
    PORT (
	ud : IN std_logic;
	reset : IN std_logic;
	clk : IN std_logic;
	Z : OUT std_logic_vector(3 DOWNTO 0)
	);
END UDasyncounter;

ARCHITECTURE structure OF UDasyncounter IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devoe : std_logic := '0';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_ud : std_logic;
SIGNAL ww_reset : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_Z : std_logic_vector(3 DOWNTO 0);
SIGNAL \clk~combout\ : std_logic;
SIGNAL \Q~8\ : std_logic;
SIGNAL \reset~combout\ : std_logic;
SIGNAL \ud~combout\ : std_logic;
SIGNAL \Q[0]\ : std_logic;
SIGNAL \Q~0\ : std_logic;
SIGNAL \Q[1]\ : std_logic;
SIGNAL \Q~1\ : std_logic;
SIGNAL \Q[2]\ : std_logic;
SIGNAL \Q~2\ : std_logic;
SIGNAL \Q[3]\ : std_logic;
SIGNAL \ALT_INV_Q[0]\ : std_logic;
SIGNAL \ALT_INV_Q[1]\ : std_logic;
SIGNAL \ALT_INV_Q[2]\ : std_logic;
SIGNAL \ALT_INV_clk~combout\ : std_logic;
SIGNAL \ALT_INV_ud~combout\ : std_logic;

BEGIN

ww_ud <= ud;
ww_reset <= reset;
ww_clk <= clk;
Z <= ww_Z;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;
\ALT_INV_Q[0]\ <= NOT \Q[0]\;
\ALT_INV_Q[1]\ <= NOT \Q[1]\;
\ALT_INV_Q[2]\ <= NOT \Q[2]\;
\ALT_INV_clk~combout\ <= NOT \clk~combout\;
\ALT_INV_ud~combout\ <= NOT \ud~combout\;

\clk~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_clk,
	combout => \clk~combout\);

\Q~8_I\ : cyclone_lcell
-- Equation(s):
-- \Q~8\ = DFFEAS(!\Q[0]\, !GLOBAL(\clk~combout\), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0F0F",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => \ALT_INV_clk~combout\,
	datac => \Q[0]\,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \Q~8\);

\reset~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_reset,
	combout => \reset~combout\);

\ud~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_ud,
	combout => \ud~combout\);

\Q[0]~I\ : cyclone_lcell
-- Equation(s):
-- \Q[0]\ = DFFEAS(!\Q[0]\, GLOBAL(\clk~combout\), !GLOBAL(\reset~combout\), , , \Q~8\, !GLOBAL(\ud~combout\), , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "3333",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => \clk~combout\,
	datab => \Q[0]\,
	datac => \Q~8\,
	aclr => \reset~combout\,
	aload => \ALT_INV_ud~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \Q[0]\);

\Q~0_I\ : cyclone_lcell
-- Equation(s):
-- \Q~0\ = DFFEAS(!\Q[1]\, !GLOBAL(\Q[0]\), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0F0F",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => \ALT_INV_Q[0]\,
	datac => \Q[1]\,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \Q~0\);

\Q[1]~I\ : cyclone_lcell
-- Equation(s):
-- \Q[1]\ = DFFEAS(!\Q[1]\, GLOBAL(\Q[0]\), !GLOBAL(\reset~combout\), , , \Q~0\, !GLOBAL(\ud~combout\), , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "5555",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => \Q[0]\,
	dataa => \Q[1]\,
	datac => \Q~0\,
	aclr => \reset~combout\,
	aload => \ALT_INV_ud~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \Q[1]\);

\Q~1_I\ : cyclone_lcell
-- Equation(s):
-- \Q~1\ = DFFEAS(!\Q[2]\, !GLOBAL(\Q[1]\), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0F0F",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => \ALT_INV_Q[1]\,
	datac => \Q[2]\,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \Q~1\);

\Q[2]~I\ : cyclone_lcell
-- Equation(s):
-- \Q[2]\ = DFFEAS(!\Q[2]\, GLOBAL(\Q[1]\), !GLOBAL(\reset~combout\), , , \Q~1\, !GLOBAL(\ud~combout\), , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "5555",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => \Q[1]\,
	dataa => \Q[2]\,
	datac => \Q~1\,
	aclr => \reset~combout\,
	aload => \ALT_INV_ud~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \Q[2]\);

\Q~2_I\ : cyclone_lcell
-- Equation(s):
-- \Q~2\ = DFFEAS(!\Q[3]\, !GLOBAL(\Q[2]\), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0F0F",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => \ALT_INV_Q[2]\,
	datac => \Q[3]\,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \Q~2\);

\Q[3]~I\ : cyclone_lcell
-- Equation(s):
-- \Q[3]\ = DFFEAS(!\Q[3]\, GLOBAL(\Q[2]\), !GLOBAL(\reset~combout\), , , \Q~2\, !GLOBAL(\ud~combout\), , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "3333",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => \Q[2]\,
	datab => \Q[3]\,
	datac => \Q~2\,
	aclr => \reset~combout\,
	aload => \ALT_INV_ud~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \Q[3]\);

\Z[0]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => \Q[0]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_Z(0));

\Z[1]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => \Q[1]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_Z(1));

\Z[2]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => \Q[2]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_Z(2));

\Z[3]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => \Q[3]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_Z(3));
END structure;