📄 udasyncounter.map.rpt
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Analysis & Synthesis report for UDasyncounter
Thu Oct 18 13:28:52 2007
Quartus II Version 7.1 Build 156 04/30/2007 SJ Web Edition
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; Table of Contents ;
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1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-----------------------------------------+
; Analysis & Synthesis Status ; Failed - Thu Oct 18 13:28:52 2007 ;
; Quartus II Version ; 7.1 Build 156 04/30/2007 SJ Web Edition ;
; Revision Name ; UDasyncounter ;
; Top-level Entity Name ; UDasyncounter ;
; Family ; Cyclone ;
+-----------------------------+-----------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Device ; EP1C6Q240C8 ; ;
; Top-level entity name ; UDasyncounter ; UDasyncounter ;
; Family name ; Cyclone ; Stratix ;
; Type of Retiming Performed During Resynthesis ; Full ; ;
; Resynthesis Optimization Effort ; Normal ; ;
; Physical Synthesis Level for Resynthesis ; Normal ; ;
; Use Generated Physical Constraints File ; On ; ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- Cyclone ; Balanced ; Balanced ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II/Cyclone III ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Retiming Meta-Stability Register Sequence Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Use smart compilation ; Off ; Off ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
+-------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+-----------------+--------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------------+--------------------------------------------------+
; UDasyncounter.vhd ; yes ; User VHDL File ; E:/VHDL programs/UDasyncounter/UDasyncounter.vhd ;
+----------------------------------+-----------------+-----------------+--------------------------------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.1 Build 156 04/30/2007 SJ Web Edition
Info: Processing started: Thu Oct 18 13:28:41 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off UDasyncounter -c UDasyncounter
Info: Found 2 design units, including 1 entities, in source file UDasyncounter.vhd
Info: Found design unit 1: UDasyncounter-beh
Info: Found entity 1: UDasyncounter
Info: Elaborating entity "UDasyncounter" for the top level hierarchy
Error (10821): HDL error at UDasyncounter.vhd(16): can't infer register for "Q[0]" because its behavior does not match any supported register model File: E:/VHDL programs/UDasyncounter/UDasyncounter.vhd Line: 16
Info (10041): Inferred latch for "Q[0]" at UDasyncounter.vhd(12)
Error (10821): HDL error at UDasyncounter.vhd(16): can't infer register for "Q[1]" because its behavior does not match any supported register model File: E:/VHDL programs/UDasyncounter/UDasyncounter.vhd Line: 16
Info (10041): Inferred latch for "Q[1]" at UDasyncounter.vhd(12)
Error (10821): HDL error at UDasyncounter.vhd(16): can't infer register for "Q[2]" because its behavior does not match any supported register model File: E:/VHDL programs/UDasyncounter/UDasyncounter.vhd Line: 16
Info (10041): Inferred latch for "Q[2]" at UDasyncounter.vhd(12)
Error (10821): HDL error at UDasyncounter.vhd(16): can't infer register for "Q[3]" because its behavior does not match any supported register model File: E:/VHDL programs/UDasyncounter/UDasyncounter.vhd Line: 16
Info (10041): Inferred latch for "Q[3]" at UDasyncounter.vhd(12)
Error (10822): HDL error at UDasyncounter.vhd(17): couldn't implement registers for assignments on this clock edge File: E:/VHDL programs/UDasyncounter/UDasyncounter.vhd Line: 17
Error (10822): HDL error at UDasyncounter.vhd(20): couldn't implement registers for assignments on this clock edge File: E:/VHDL programs/UDasyncounter/UDasyncounter.vhd Line: 20
Error (10822): HDL error at UDasyncounter.vhd(23): couldn't implement registers for assignments on this clock edge File: E:/VHDL programs/UDasyncounter/UDasyncounter.vhd Line: 23
Error (10822): HDL error at UDasyncounter.vhd(26): couldn't implement registers for assignments on this clock edge File: E:/VHDL programs/UDasyncounter/UDasyncounter.vhd Line: 26
Error (10822): HDL error at UDasyncounter.vhd(30): couldn't implement registers for assignments on this clock edge File: E:/VHDL programs/UDasyncounter/UDasyncounter.vhd Line: 30
Error (10822): HDL error at UDasyncounter.vhd(33): couldn't implement registers for assignments on this clock edge File: E:/VHDL programs/UDasyncounter/UDasyncounter.vhd Line: 33
Error (10822): HDL error at UDasyncounter.vhd(36): couldn't implement registers for assignments on this clock edge File: E:/VHDL programs/UDasyncounter/UDasyncounter.vhd Line: 36
Error (10822): HDL error at UDasyncounter.vhd(39): couldn't implement registers for assignments on this clock edge File: E:/VHDL programs/UDasyncounter/UDasyncounter.vhd Line: 39
Error: Can't elaborate top-level user hierarchy
Error: Quartus II Analysis & Synthesis was unsuccessful. 13 errors, 0 warnings
Info: Allocated 144 megabytes of memory during processing
Error: Processing ended: Thu Oct 18 13:28:54 2007
Error: Elapsed time: 00:00:13
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