📄 udasyncounter.map.eqn
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--Q[0] is Q[0]
--operation mode is normal
Q[0]_lut_out = !Q[0];
Q[0] = DFFEAS(Q[0]_lut_out, clk, !reset, , , A1L10Q, !ud, , );
--Q[1] is Q[1]
--operation mode is normal
Q[1]_lut_out = !Q[1];
Q[1] = DFFEAS(Q[1]_lut_out, Q[0], !reset, , , A1L7Q, !ud, , );
--Q[2] is Q[2]
--operation mode is normal
Q[2]_lut_out = !Q[2];
Q[2] = DFFEAS(Q[2]_lut_out, Q[1], !reset, , , A1L8Q, !ud, , );
--Q[3] is Q[3]
--operation mode is normal
Q[3]_lut_out = !Q[3];
Q[3] = DFFEAS(Q[3]_lut_out, Q[2], !reset, , , A1L9Q, !ud, , );
--A1L10Q is Q~8
--operation mode is normal
A1L10Q_lut_out = !Q[0];
A1L10Q = DFFEAS(A1L10Q_lut_out, !clk, VCC, , , , , , );
--A1L7Q is Q~0
--operation mode is normal
A1L7Q_lut_out = !Q[1];
A1L7Q = DFFEAS(A1L7Q_lut_out, !Q[0], VCC, , , , , , );
--A1L8Q is Q~1
--operation mode is normal
A1L8Q_lut_out = !Q[2];
A1L8Q = DFFEAS(A1L8Q_lut_out, !Q[1], VCC, , , , , , );
--A1L9Q is Q~2
--operation mode is normal
A1L9Q_lut_out = !Q[3];
A1L9Q = DFFEAS(A1L9Q_lut_out, !Q[2], VCC, , , , , , );
--clk is clk
--operation mode is input
clk = INPUT();
--reset is reset
--operation mode is input
reset = INPUT();
--ud is ud
--operation mode is input
ud = INPUT();
--Z[0] is Z[0]
--operation mode is output
Z[0] = OUTPUT(Q[0]);
--Z[1] is Z[1]
--operation mode is output
Z[1] = OUTPUT(Q[1]);
--Z[2] is Z[2]
--operation mode is output
Z[2] = OUTPUT(Q[2]);
--Z[3] is Z[3]
--operation mode is output
Z[3] = OUTPUT(Q[3]);
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