udasyncounter.tan.talkback.xml

Up-down Asynchronous counter in Behavioral Model

<!--
This XML file (created on Wed Oct 10 15:59:10 2007) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to www.altera.com/products/software/download/dnl-download_license.html
-->
<talkback>
<ver>5.1</ver>
<schema>quartus_version_5.1_build_176.xsd</schema><license>
	<host_id>000000000000</host_id>
	<nic_id>000000000000</nic_id>
	<cdrive_id>14f82eee</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>5.1</version>
	<build>Build 176</build>
	<binary_type>32</binary_type>
	<module>quartus_tan.exe</module>
	<edition>Web Edition</edition>
	<compilation_end_time>Wed Oct 10 15:59:11 2007</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>1</proc_count>
		<cpu_freq units="MHz">2400</cpu_freq>
	</cpu>
	<ram units="MB">255</ram>
</machine>
<top_file>C:/altera/quartus51/UDasyncounter/UDasyncounter</top_file>
<mep_data>
	<command_line>quartus_tan --read_settings_files=off --write_settings_files=off UDasyncounter -c UDasyncounter --timing_analysis_only</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<messages>
	<warning>Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew</warning>
	<warning>Warning: Found pins functioning as undefined clocks and/or memory enables</warning>
	<info>Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings</info>
	<info>Info: Elapsed time: 00:00:01</info>
	<info>Info: Processing ended: Wed Oct 10 15:59:10 2007</info>
	<info>Info: tco from clock &quot;clk&quot; to destination pin &quot;Z[3]&quot; through register &quot;Q[3]&quot; is 21.009 ns</info>
	<info>Info: + Longest register to pin delay is 3.268 ns</info>
</messages>
<clock_settings_summary>
	<row>
		<clock_node_name>clk</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
</clock_settings_summary>
<performance>
	<nonclk>
		<type>Worst-case tco</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>21.009 ns</actual>
	</nonclk>
	<clk>
		<name>clk</name>
		<slack>N/A</slack>
		<required>None</required>
		<actual>Restricted to 275.03 MHz ( period = 3.636 ns )</actual>
	</clk>
</performance>
<compile_id>33CD2BBD</compile_id>
</talkback>