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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
Entity Boothsmul is
port(a,b : in signed(22 downto 0);
en : in std_logic;
c: out signed(45 downto 0));
end Boothsmul;
Architecture beh of Boothsmul is
begin
process(en)
variable acc : signed(45 downto 0):=(others=>'0');
variable ltwolsb : signed(1 downto 0) := "00";
--variable count:integer := 8;
begin
if en = '1' and en'event then
acc(22 downto 0) := acc(22 downto 0) + b;
for i in 0 to 22 loop
-- wait until clk = '1' and clk'event;
ltwolsb := acc(0) & ltwolsb(1);
if ltwolsb(0) = '1' and ltwolsb(1) = '0' then
acc(45 downto 23) := acc(45 downto 23) + a;
elsif ltwolsb(0) = '0' and ltwolsb(1) = '1' then
acc(45 downto 23) := acc(45 downto 23) - a;
end if;
acc := acc(45) & acc(45 downto 1);
-- count := count - 1;
end loop;
end if;
c <= acc;
end process;
end beh;
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