clock.rpt

vhdl实现时钟和闹钟功能

         #  hourlow2
         #  hourlow1
         # !hourlow0;

-- Node name is '~355~1' 
-- Equation name is '~355~1', location is LC3_B23, type is buried.
-- synthesized logic cell 
!_LC3_B23 = _LC3_B23~NOT;
_LC3_B23~NOT = LCELL( _EQ042);
  _EQ042 =  hourlow3
         # !_LC3_B29;

-- Node name is ':355' 
-- Equation name is '_LC1_B23', type is buried 
!_LC1_B23 = _LC1_B23~NOT;
_LC1_B23~NOT = LCELL( _EQ043);
  _EQ043 = !_LC3_B23
         # !hourhigh1
         #  hourhigh0
         #  hourlow2;

-- Node name is ':400' 
-- Equation name is '_LC2_C36', type is buried 
_LC2_C36 = LCELL( _EQ044);
  _EQ044 = !week0 & !week1 & !week2 &  week3;

-- Node name is ':409' 
-- Equation name is '_LC1_C36', type is buried 
!_LC1_C36 = _LC1_C36~NOT;
_LC1_C36~NOT = LCELL( _EQ045);
  _EQ045 =  week0
         # !week1
         #  week3
         # !week2;

-- Node name is '~567~1' 
-- Equation name is '~567~1', location is LC4_C36, type is buried.
-- synthesized logic cell 
_LC4_C36 = LCELL( _EQ046);
  _EQ046 =  _LC1_B23 & !_LC1_C36 & !_LC2_C36;

-- Node name is '~732~1' 
-- Equation name is '~732~1', location is LC3_B19, type is buried.
-- synthesized logic cell 
_LC3_B19 = LCELL( _EQ047);
  _EQ047 = !_LC1_B23 & !_LC5_B23 &  _LC6_B36;

-- Node name is ':844' 
-- Equation name is '_LC2_B19', type is buried 
_LC2_B19 = LCELL( _EQ048);
  _EQ048 =  _LC4_B35 &  minhigh0 &  minhigh1 & !minhigh2
         # !minhigh0 &  minhigh2
         # !_LC4_B35 &  minhigh2;

-- Node name is '~845~1' 
-- Equation name is '~845~1', location is LC5_B36, type is buried.
-- synthesized logic cell 
_LC5_B36 = LCELL( _EQ049);
  _EQ049 =  _LC4_B35 & !_LC6_B36;

-- Node name is ':989' 
-- Equation name is '_LC8_B35', type is buried 
_LC8_B35 = LCELL( _EQ050);
  _EQ050 =  _LC3_B21 & !_LC4_B35 &  _LC6_B35
         # !_LC3_B21 &  minlow3;

-- Node name is ':995' 
-- Equation name is '_LC5_B35', type is buried 
_LC5_B35 = LCELL( _EQ051);
  _EQ051 = !_LC3_B35 & !_LC4_B35 &  minlow2
         #  _LC3_B21 &  _LC3_B35 & !_LC4_B35 & !minlow2
         # !_LC3_B21 &  minlow2;

-- Node name is ':1001' 
-- Equation name is '_LC7_B21', type is buried 
_LC7_B21 = LCELL( _EQ052);
  _EQ052 = !_LC4_B35 & !minlow0 &  minlow1
         #  _LC3_B21 & !_LC4_B35 &  minlow0 & !minlow1
         # !_LC3_B21 &  minlow1;

-- Node name is ':1013' 
-- Equation name is '_LC4_B19', type is buried 
_LC4_B19 = LCELL( _EQ053);
  _EQ053 =  _LC2_B19 &  _LC3_B21
         # !_LC3_B21 &  minhigh2;

-- Node name is ':1175' 
-- Equation name is '_LC6_B21', type is buried 
_LC6_B21 = LCELL( _EQ054);
  _EQ054 =  _LC8_E33 &  sechigh0 &  sechigh1 & !sechigh2
         # !sechigh0 &  sechigh2
         # !_LC8_E33 &  sechigh2;

-- Node name is ':1181' 
-- Equation name is '_LC5_B21', type is buried 
_LC5_B21 = LCELL( _EQ055);
  _EQ055 = !_LC8_E33 &  sechigh1
         # !_LC3_B21 & !sechigh0 &  sechigh1
         # !_LC3_B21 &  _LC8_E33 &  sechigh0 & !sechigh1;

-- Node name is '~1223~1' 
-- Equation name is '~1223~1', location is LC7_B36, type is buried.
-- synthesized logic cell 
_LC7_B36 = LCELL( _EQ056);
  _EQ056 =  _LC5_B36 & !minhigh0 &  minhigh1
         #  _LC3_B36 &  minhigh1;

-- Node name is '~1229~1' 
-- Equation name is '~1229~1', location is LC3_B36, type is buried.
-- synthesized logic cell 
!_LC3_B36 = _LC3_B36~NOT;
_LC3_B36~NOT = LCELL( _EQ057);
  _EQ057 =  _LC1_B36 &  _LC4_B35;

-- Node name is '~1235~1' 
-- Equation name is '~1235~1', location is LC4_B36, type is buried.
-- synthesized logic cell 
!_LC4_B36 = _LC4_B36~NOT;
_LC4_B36~NOT = LCELL( _EQ058);
  _EQ058 =  _LC1_B36 &  _LC4_B35 & !_LC5_B23 &  _LC6_B36;

-- Node name is '~1235~2' 
-- Equation name is '~1235~2', location is LC3_C36, type is buried.
-- synthesized logic cell 
_LC3_C36 = LCELL( _EQ059);
  _EQ059 =  week1 &  week2 & !week3;

-- Node name is '~1235~3' 
-- Equation name is '~1235~3', location is LC5_C36, type is buried.
-- synthesized logic cell 
_LC5_C36 = LCELL( _EQ060);
  _EQ060 =  _LC1_B23 & !_LC2_C36 &  _LC3_C36 & !_LC4_B36;

-- Node name is '~1235~4' 
-- Equation name is '~1235~4', location is LC7_C36, type is buried.
-- synthesized logic cell 
_LC7_C36 = LCELL( _EQ061);
  _EQ061 = !week1
         # !week0
         # !week2;

-- Node name is '~1235~5' 
-- Equation name is '~1235~5', location is LC8_C36, type is buried.
-- synthesized logic cell 
_LC8_C36 = LCELL( _EQ062);
  _EQ062 = !_LC2_C36 &  _LC7_C36
         #  _LC4_B36
         # !_LC1_B23;

-- Node name is '~1241~1' 
-- Equation name is '~1241~1', location is LC6_C34, type is buried.
-- synthesized logic cell 
_LC6_C34 = LCELL( _EQ063);
  _EQ063 =  _LC4_C36 & !week1
         #  _LC4_C36 & !week0
         #  _LC5_C34;

-- Node name is '~1247~1' 
-- Equation name is '~1247~1', location is LC1_C34, type is buried.
-- synthesized logic cell 
_LC1_C34 = LCELL( _EQ064);
  _EQ064 =  _LC4_C36 & !week0
         #  _LC5_C34;

-- Node name is '~1253~1' 
-- Equation name is '~1253~1', location is LC5_C34, type is buried.
-- synthesized logic cell 
!_LC5_C34 = _LC5_C34~NOT;
_LC5_C34~NOT = LCELL( _EQ065);
  _EQ065 =  _LC1_B23 & !_LC4_B36;

-- Node name is '~1253~2' 
-- Equation name is '~1253~2', location is LC2_C31, type is buried.
-- synthesized logic cell 
_LC2_C31 = LCELL( _EQ066);
  _EQ066 =  _LC2_C36
         # !_LC1_C36 & !week0;

-- Node name is '~1259~1' 
-- Equation name is '~1259~1', location is LC7_B23, type is buried.
-- synthesized logic cell 
_LC7_B23 = LCELL( _EQ067);
  _EQ067 = !hourlow2 &  _LC3_B19
         #  _LC3_B19 & !_LC3_B29
         #  _LC6_B19;

-- Node name is '~1265~1' 
-- Equation name is '~1265~1', location is LC8_B29, type is buried.
-- synthesized logic cell 
_LC8_B29 = LCELL( _EQ068);
  _EQ068 =  _LC3_B19 & !_LC3_B29
         #  _LC6_B19;

-- Node name is '~1271~1' 
-- Equation name is '~1271~1', location is LC1_B29, type is buried.
-- synthesized logic cell 
_LC1_B29 = LCELL( _EQ069);
  _EQ069 = !hourlow0 &  hourlow1 &  _LC3_B19
         #  hourlow1 &  _LC6_B19;

-- Node name is '~1277~1' 
-- Equation name is '~1277~1', location is LC6_B19, type is buried.
-- synthesized logic cell 
!_LC6_B19 = _LC6_B19~NOT;
_LC6_B19~NOT = LCELL( _EQ070);
  _EQ070 = !_LC3_B36 &  _LC6_B36;

-- Node name is '~1283~1' 
-- Equation name is '~1283~1', location is LC8_B19, type is buried.
-- synthesized logic cell 
_LC8_B19 = LCELL( _EQ071);
  _EQ071 = !hourhigh0 &  _LC5_B23
         # !_LC1_B23 & !_LC5_B23
         #  _LC6_B19;



Project Information                               c:\max2work\clock0\clock.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 27,912K