📄 clock.rpt
字号:
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: c:\max2work\clock0\clock.rpt
clock
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
15 - - B -- OUTPUT 0 1 0 0 hourhdis0
68 - - - 24 OUTPUT 0 1 0 0 hourhdis1
70 - - - 22 OUTPUT 0 1 0 0 hourldis0
140 - - B -- OUTPUT 0 1 0 0 hourldis1
141 - - B -- OUTPUT 0 1 0 0 hourldis2
69 - - - 23 OUTPUT 0 1 0 0 hourldis3
14 - - B -- OUTPUT 0 1 0 0 minhdis0
13 - - B -- OUTPUT 0 1 0 0 minhdis1
144 - - B -- OUTPUT 0 1 0 0 minhdis2
12 - - B -- OUTPUT 0 1 0 0 minldis0
142 - - B -- OUTPUT 0 1 0 0 minldis1
207 - - - 35 OUTPUT 0 1 0 0 minldis2
53 - - - 36 OUTPUT 0 1 0 0 minldis3
204 - - - 33 OUTPUT 0 1 0 0 sechdis0
190 - - - 22 OUTPUT 0 1 0 0 sechdis1
71 - - - 21 OUTPUT 0 1 0 0 sechdis2
39 - - E -- OUTPUT 0 1 0 0 secldis0
36 - - E -- OUTPUT 0 1 0 0 secldis1
40 - - E -- OUTPUT 0 1 0 0 secldis2
38 - - E -- OUTPUT 0 1 0 0 secldis3
16 - - C -- OUTPUT 0 1 0 0 weekdis0
17 - - C -- OUTPUT 0 1 0 0 weekdis1
18 - - C -- OUTPUT 0 1 0 0 weekdis2
24 - - C -- OUTPUT 0 1 0 0 weekdis3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\max2work\clock0\clock.rpt
clock
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - B 29 OR2 ! 0 2 0 4 |LPM_ADD_SUB:532|addcore:adder|:59
- 3 - B 35 AND2 0 2 0 1 |LPM_ADD_SUB:798|addcore:adder|:59
- 6 - B 35 OR2 0 4 0 1 |LPM_ADD_SUB:798|addcore:adder|:77
- 2 - E 33 AND2 0 2 0 1 |LPM_ADD_SUB:1129|addcore:adder|:59
- 7 - E 33 AND2 0 3 0 1 |LPM_ADD_SUB:1129|addcore:adder|:63
- 4 - E 33 DFFE + 1 2 1 1 seclow3 (:51)
- 6 - E 33 DFFE + 1 2 1 2 seclow2 (:52)
- 1 - E 33 DFFE + 1 2 1 3 seclow1 (:53)
- 5 - E 33 DFFE + 1 0 1 4 seclow0 (:54)
- 2 - B 21 DFFE + 1 1 1 2 sechigh2 (:55)
- 8 - B 21 DFFE + 1 1 1 3 sechigh1 (:56)
- 3 - E 33 DFFE + 1 1 1 3 sechigh0 (:57)
- 1 - B 35 DFFE + 1 2 1 3 minlow3 (:58)
- 7 - B 35 DFFE + 1 2 1 3 minlow2 (:59)
- 4 - B 21 DFFE + 1 2 1 4 minlow1 (:60)
- 2 - B 35 DFFE + 1 2 1 4 minlow0 (:61)
- 1 - B 19 DFFE + 1 2 1 3 minhigh2 (:62)
- 2 - B 36 DFFE + 1 3 1 4 minhigh1 (:63)
- 5 - B 19 DFFE + 1 1 1 4 minhigh0 (:64)
- 2 - B 23 DFFE + 1 2 1 2 hourlow3 (:65)
- 5 - B 29 DFFE + 1 2 1 4 hourlow2 (:66)
- 6 - B 29 DFFE + 1 3 1 4 hourlow1 (:67)
- 1 - B 21 DFFE + 1 1 1 4 hourlow0 (:68)
- 6 - B 23 DFFE + 1 2 1 2 hourhigh1 (:69)
- 7 - B 19 DFFE + 1 2 1 3 hourhigh0 (:70)
- 6 - C 36 DFFE + 1 2 1 3 week3 (:71)
- 3 - C 34 DFFE + 1 2 1 5 week2 (:72)
- 2 - C 34 DFFE + 1 2 1 7 week1 (:73)
- 1 - C 31 DFFE + 1 2 1 8 week0 (:74)
- 1 - B 36 AND2 s 0 2 0 3 ~263~1
- 8 - B 36 AND2 s 0 4 0 1 ~263~2
- 2 - B 29 AND2 s 0 2 0 1 ~263~3
- 7 - B 29 AND2 s 0 3 0 1 ~263~4
- 4 - B 23 AND2 s 0 4 0 1 ~263~5
- 8 - B 23 AND2 s 0 4 0 1 ~263~6
- 4 - C 34 AND2 s 0 4 0 1 ~263~7
- 7 - C 34 AND2 s 0 2 0 1 ~263~8
- 8 - C 34 AND2 s 0 4 0 1 ~263~9
- 8 - E 33 OR2 ! 0 4 0 12 :263
- 3 - B 21 OR2 ! 0 3 0 7 :279
- 4 - B 35 OR2 ! 0 4 0 8 :295
- 6 - B 36 OR2 ! 0 3 0 5 :311
- 4 - B 29 AND2 s 0 2 0 1 ~336~1
- 5 - B 23 OR2 ! 0 4 0 5 :336
- 3 - B 23 OR2 s ! 0 2 0 2 ~355~1
- 1 - B 23 OR2 ! 0 4 0 6 :355
- 2 - C 36 AND2 0 4 0 4 :400
- 1 - C 36 OR2 ! 0 4 0 2 :409
- 4 - C 36 AND2 s 0 3 0 4 ~567~1
- 3 - B 19 AND2 s 0 3 0 6 ~732~1
- 2 - B 19 OR2 0 4 0 1 :844
- 5 - B 36 AND2 s 0 2 0 1 ~845~1
- 8 - B 35 OR2 0 4 0 1 :989
- 5 - B 35 OR2 0 4 0 1 :995
- 7 - B 21 OR2 0 4 0 1 :1001
- 4 - B 19 OR2 0 3 0 1 :1013
- 6 - B 21 OR2 0 4 0 1 :1175
- 5 - B 21 OR2 0 4 0 1 :1181
- 7 - B 36 OR2 s 0 4 0 1 ~1223~1
- 3 - B 36 AND2 s ! 0 2 0 6 ~1229~1
- 4 - B 36 AND2 s ! 0 4 0 5 ~1235~1
- 3 - C 36 AND2 s 0 3 0 1 ~1235~2
- 5 - C 36 AND2 s 0 4 0 1 ~1235~3
- 7 - C 36 OR2 s 0 3 0 1 ~1235~4
- 8 - C 36 OR2 s 0 4 0 1 ~1235~5
- 6 - C 34 OR2 s 0 4 0 1 ~1241~1
- 1 - C 34 OR2 s 0 3 0 1 ~1247~1
- 5 - C 34 AND2 s ! 0 2 0 3 ~1253~1
- 2 - C 31 OR2 s 0 3 0 1 ~1253~2
- 7 - B 23 OR2 s 0 4 0 1 ~1259~1
- 8 - B 29 OR2 s 0 3 0 1 ~1265~1
- 1 - B 29 OR2 s 0 4 0 1 ~1271~1
- 6 - B 19 AND2 s ! 0 2 0 7 ~1277~1
- 8 - B 19 OR2 s 0 4 0 1 ~1283~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: c:\max2work\clock0\clock.rpt
clock
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 23/144( 15%) 0/ 72( 0%) 13/ 72( 18%) 2/16( 12%) 8/16( 50%) 0/16( 0%)
C: 11/144( 7%) 0/ 72( 0%) 3/ 72( 4%) 4/16( 25%) 4/16( 25%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 3/144( 2%) 0/ 72( 0%) 2/ 72( 2%) 1/16( 6%) 4/16( 25%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
21: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
22: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
23: 3/24( 12%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
24: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
25: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
28: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
33: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
34: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
35: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
36: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\max2work\clock0\clock.rpt
clock
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 24 clk
Device-Specific Information: c:\max2work\clock0\clock.rpt
clock
** EQUATIONS **
clk : INPUT;
hourhset0 : INPUT;
hourhset1 : INPUT;
hourlset0 : INPUT;
hourlset1 : INPUT;
hourlset2 : INPUT;
hourlset3 : INPUT;
minhset0 : INPUT;
minhset1 : INPUT;
minhset2 : INPUT;
minlset0 : INPUT;
minlset1 : INPUT;
minlset2 : INPUT;
minlset3 : INPUT;
sechset0 : INPUT;
sechset1 : INPUT;
sechset2 : INPUT;
seclset0 : INPUT;
seclset1 : INPUT;
seclset2 : INPUT;
seclset3 : INPUT;
settime : INPUT;
weekset0 : INPUT;
weekset1 : INPUT;
weekset2 : INPUT;
weekset3 : INPUT;
-- Node name is 'hourhdis0'
-- Equation name is 'hourhdis0', type is output
hourhdis0 = hourhigh0;
-- Node name is 'hourhdis1'
-- Equation name is 'hourhdis1', type is output
hourhdis1 = hourhigh1;
-- Node name is ':70' = 'hourhigh0'
-- Equation name is 'hourhigh0', location is LC7_B19, type is buried.
hourhigh0 = DFFE( _EQ001, GLOBAL( clk), !(GLOBAL( settime) & !hourhset0), !(GLOBAL( settime) & hourhset0), VCC);
_EQ001 = hourhigh0 & !_LC5_B23
# hourhigh0 & _LC6_B19
# !hourhigh0 & _LC5_B23 & !_LC6_B19;
-- Node name is ':69' = 'hourhigh1'
-- Equation name is 'hourhigh1', location is LC6_B23, type is buried.
hourhigh1 = DFFE( _EQ002, GLOBAL( clk), !(GLOBAL( settime) & !hourhset1), !(GLOBAL( settime) & hourhset1), VCC);
_EQ002 = hourhigh1 & _LC8_B19
# _LC8_B23;
-- Node name is 'hourldis0'
-- Equation name is 'hourldis0', type is output
hourldis0 = hourlow0;
-- Node name is 'hourldis1'
-- Equation name is 'hourldis1', type is output
hourldis1 = hourlow1;
-- Node name is 'hourldis2'
-- Equation name is 'hourldis2', type is output
hourldis2 = hourlow2;
-- Node name is 'hourldis3'
-- Equation name is 'hourldis3', type is output
hourldis3 = hourlow3;
-- Node name is ':68' = 'hourlow0'
-- Equation name is 'hourlow0', location is LC1_B21, type is buried.
hourlow0 = DFFE( _EQ003, GLOBAL( clk), !(GLOBAL( settime) & !hourlset0), !(GLOBAL( settime) & hourlset0), VCC);
_EQ003 = hourlow0 & _LC6_B19
# !hourlow0 & !_LC6_B19;
-- Node name is ':67' = 'hourlow1'
-- Equation name is 'hourlow1', location is LC6_B29, type is buried.
hourlow1 = DFFE( _EQ004, GLOBAL( clk), !(GLOBAL( settime) & !hourlset1), !(GLOBAL( settime) & hourlset1), VCC);
_EQ004 = _LC1_B29
# _LC2_B29 & _LC4_B29;
-- Node name is ':66' = 'hourlow2'
-- Equation name is 'hourlow2', location is LC5_B29, type is buried.
hourlow2 = DFFE( _EQ005, GLOBAL( clk), !(GLOBAL( settime) & !hourlset2), !(GLOBAL( settime) & hourlset2), VCC);
_EQ005 = !hourlow2 & _LC7_B29
# hourlow2 & _LC8_B29;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -