dou.vhd

来自「vhdl实现时钟和闹钟功能」· VHDL 代码 · 共 41 行

library ieee;

use ieee.std_logic_1164.all;



entity dou is

port(din,clk:in std_logic;

        dout:out std_logic);

end dou;



architecture beha of dou is

signal x,y:std_logic;

begin

process(clk)

begin

  if clk'event and clk='1' then

         x<=din;

         y<=x;

  end if;

dout<=x and (not y);

end process;

end beha;