control.rpt

vhdl实现时钟和闹钟功能

  _EQ008 = !alarm_adjsta0 & !alarm_adjsta1 & !alarm_adjsta2 & 
              alarm_hourhset0 &  mode;

-- Node name is 'alarm_hourlset0' = 'alarm_hourlow0' 
-- Equation name is 'alarm_hourlset0', location is LC056, type is output.
 alarm_hourlset0 = TFFE( _EQ009, GLOBAL( keyup),  VCC,  VCC,  VCC);
  _EQ009 =  alarm_adjsta0 & !alarm_adjsta1 & !alarm_adjsta2 &  mode;

-- Node name is 'alarm_hourlset1' = 'alarm_hourlow1' 
-- Equation name is 'alarm_hourlset1', location is LC057, type is output.
 alarm_hourlset1 = TFFE( _EQ010, GLOBAL( keyup),  VCC,  VCC,  VCC);
  _EQ010 =  alarm_adjsta0 & !alarm_adjsta1 & !alarm_adjsta2 & 
              alarm_hourlset0 &  mode;

-- Node name is 'alarm_hourlset2' = 'alarm_hourlow2' 
-- Equation name is 'alarm_hourlset2', location is LC059, type is output.
 alarm_hourlset2 = TFFE( _EQ011, GLOBAL( keyup),  VCC,  VCC,  VCC);
  _EQ011 =  alarm_adjsta0 & !alarm_adjsta1 & !alarm_adjsta2 & 
              alarm_hourlset0 &  alarm_hourlset1 &  mode;

-- Node name is 'alarm_hourlset3' = 'alarm_hourlow3' 
-- Equation name is 'alarm_hourlset3', location is LC060, type is output.
 alarm_hourlset3 = TFFE( _EQ012, GLOBAL( keyup),  VCC,  VCC,  VCC);
  _EQ012 =  alarm_adjsta0 & !alarm_adjsta1 & !alarm_adjsta2 & 
              alarm_hourlset0 &  alarm_hourlset1 &  alarm_hourlset2 &  mode;

-- Node name is 'alarm_minhset0' = 'alarm_minhigh0' 
-- Equation name is 'alarm_minhset0', location is LC052, type is output.
 alarm_minhset0 = TFFE( _EQ013, GLOBAL( keyup),  VCC,  VCC,  VCC);
  _EQ013 = !alarm_adjsta0 &  alarm_adjsta1 & !alarm_adjsta2 &  mode;

-- Node name is 'alarm_minhset1' = 'alarm_minhigh1' 
-- Equation name is 'alarm_minhset1', location is LC053, type is output.
 alarm_minhset1 = TFFE( _EQ014, GLOBAL( keyup),  VCC,  VCC,  VCC);
  _EQ014 = !alarm_adjsta0 &  alarm_adjsta1 & !alarm_adjsta2 &  alarm_minhset0 & 
              mode;

-- Node name is 'alarm_minhset2' = 'alarm_minhigh2' 
-- Equation name is 'alarm_minhset2', location is LC064, type is output.
 alarm_minhset2 = TFFE( _EQ015, GLOBAL( keyup),  VCC,  VCC,  VCC);
  _EQ015 = !alarm_adjsta0 &  alarm_adjsta1 & !alarm_adjsta2 &  alarm_minhset0 & 
              alarm_minhset1 &  mode;

-- Node name is 'alarm_minlset0' = 'alarm_minlow0' 
-- Equation name is 'alarm_minlset0', location is LC054, type is output.
 alarm_minlset0 = TFFE( _EQ016, GLOBAL( keyup),  VCC,  VCC,  VCC);
  _EQ016 =  alarm_adjsta0 &  alarm_adjsta1 & !alarm_adjsta2 &  mode;

-- Node name is 'alarm_minlset1' = 'alarm_minlow1' 
-- Equation name is 'alarm_minlset1', location is LC049, type is output.
 alarm_minlset1 = TFFE( _EQ017, GLOBAL( keyup),  VCC,  VCC,  VCC);
  _EQ017 =  alarm_adjsta0 &  alarm_adjsta1 & !alarm_adjsta2 &  alarm_minlset0 & 
              mode;

-- Node name is 'alarm_minlset2' = 'alarm_minlow2' 
-- Equation name is 'alarm_minlset2', location is LC051, type is output.
 alarm_minlset2 = TFFE( _EQ018, GLOBAL( keyup),  VCC,  VCC,  VCC);
  _EQ018 =  alarm_adjsta0 &  alarm_adjsta1 & !alarm_adjsta2 &  alarm_minlset0 & 
              alarm_minlset1 &  mode;

-- Node name is 'alarm_minlset3' = 'alarm_minlow3' 
-- Equation name is 'alarm_minlset3', location is LC061, type is output.
 alarm_minlset3 = TFFE( _EQ019, GLOBAL( keyup),  VCC,  VCC,  VCC);
  _EQ019 =  alarm_adjsta0 &  alarm_adjsta1 & !alarm_adjsta2 &  alarm_minlset0 & 
              alarm_minlset1 &  alarm_minlset2 &  mode;

-- Node name is 'hourhset0' = 'hourhigh0' 
-- Equation name is 'hourhset0', location is LC020, type is output.
 hourhset0 = TFFE( _EQ020, GLOBAL( keyup),  VCC,  VCC,  VCC);
  _EQ020 =  adjsta0 & !adjsta1 & !adjsta2 & !mode;

-- Node name is 'hourhset1' = 'hourhigh1' 
-- Equation name is 'hourhset1', location is LC046, type is output.
 hourhset1 = TFFE( _EQ021, GLOBAL( keyup),  VCC,  VCC,  VCC);
  _EQ021 =  adjsta0 & !adjsta1 & !adjsta2 &  hourhset0 & !mode;

-- Node name is 'hourlset0' = 'hourlow0' 
-- Equation name is 'hourlset0', location is LC040, type is output.
 hourlset0 = TFFE( _EQ022, GLOBAL( keyup),  VCC,  VCC,  VCC);
  _EQ022 = !adjsta0 &  adjsta1 & !adjsta2 & !mode;

-- Node name is 'hourlset1' = 'hourlow1' 
-- Equation name is 'hourlset1', location is LC041, type is output.
 hourlset1 = TFFE( _EQ023, GLOBAL( keyup),  VCC,  VCC,  VCC);
  _EQ023 = !adjsta0 &  adjsta1 & !adjsta2 &  hourlset0 & !mode;

-- Node name is 'hourlset2' = 'hourlow2' 
-- Equation name is 'hourlset2', location is LC044, type is output.
 hourlset2 = TFFE( _EQ024, GLOBAL( keyup),  VCC,  VCC,  VCC);
  _EQ024 = !adjsta0 &  adjsta1 & !adjsta2 &  hourlset0 &  hourlset1 & !mode;

-- Node name is 'hourlset3' = 'hourlow3' 
-- Equation name is 'hourlset3', location is LC036, type is output.
 hourlset3 = TFFE( _EQ025, GLOBAL( keyup),  VCC,  VCC,  VCC);
  _EQ025 = !adjsta0 &  adjsta1 & !adjsta2 &  hourlset0 &  hourlset1 & 
              hourlset2 & !mode;

-- Node name is 'minhset0' = 'minhigh0' 
-- Equation name is 'minhset0', location is LC038, type is output.
 minhset0 = TFFE( _EQ026, GLOBAL( keyup),  VCC,  VCC,  VCC);
  _EQ026 =  adjsta0 &  adjsta1 & !adjsta2 & !mode;

-- Node name is 'minhset1' = 'minhigh1' 
-- Equation name is 'minhset1', location is LC037, type is output.
 minhset1 = TFFE( _EQ027, GLOBAL( keyup),  VCC,  VCC,  VCC);
  _EQ027 =  adjsta0 &  adjsta1 & !adjsta2 &  minhset0 & !mode;

-- Node name is 'minhset2' = 'minhigh2' 
-- Equation name is 'minhset2', location is LC048, type is output.
 minhset2 = TFFE( _EQ028, GLOBAL( keyup),  VCC,  VCC,  VCC);
  _EQ028 =  adjsta0 &  adjsta1 & !adjsta2 &  minhset0 &  minhset1 & !mode;

-- Node name is 'minlset0' = 'minlow0' 
-- Equation name is 'minlset0', location is LC035, type is output.
 minlset0 = TFFE( _EQ029, GLOBAL( keyup),  VCC,  VCC,  VCC);
  _EQ029 = !adjsta0 & !adjsta1 &  adjsta2 & !mode;

-- Node name is 'minlset1' = 'minlow1' 
-- Equation name is 'minlset1', location is LC019, type is output.
 minlset1 = TFFE( _EQ030, GLOBAL( keyup),  VCC,  VCC,  VCC);
  _EQ030 = !adjsta0 & !adjsta1 &  adjsta2 &  minlset0 & !mode;

-- Node name is 'minlset2' = 'minlow2' 
-- Equation name is 'minlset2', location is LC017, type is output.
 minlset2 = TFFE( _EQ031, GLOBAL( keyup),  VCC,  VCC,  VCC);
  _EQ031 = !adjsta0 & !adjsta1 &  adjsta2 &  minlset0 &  minlset1 & !mode;

-- Node name is 'minlset3' = 'minlow3' 
-- Equation name is 'minlset3', location is LC024, type is output.
 minlset3 = TFFE( _EQ032, GLOBAL( keyup),  VCC,  VCC,  VCC);
  _EQ032 = !adjsta0 & !adjsta1 &  adjsta2 &  minlset0 &  minlset1 &  minlset2 & 
             !mode;

-- Node name is 'sechset0' = 'sechigh0' 
-- Equation name is 'sechset0', location is LC033, type is output.
 sechset0 = TFFE( _EQ033, GLOBAL( keyup),  VCC,  VCC,  VCC);
  _EQ033 =  adjsta0 & !adjsta1 &  adjsta2 & !mode;

-- Node name is 'sechset1' = 'sechigh1' 
-- Equation name is 'sechset1', location is LC025, type is output.
 sechset1 = TFFE( _EQ034, GLOBAL( keyup),  VCC,  VCC,  VCC);
  _EQ034 =  adjsta0 & !adjsta1 &  adjsta2 & !mode &  sechset0;

-- Node name is 'sechset2' = 'sechigh2' 
-- Equation name is 'sechset2', location is LC032, type is output.
 sechset2 = TFFE( _EQ035, GLOBAL( keyup),  VCC,  VCC,  VCC);
  _EQ035 =  adjsta0 & !adjsta1 &  adjsta2 & !mode &  sechset0 &  sechset1;

-- Node name is 'seclset0' = 'seclow0' 
-- Equation name is 'seclset0', location is LC043, type is output.
 seclset0 = TFFE( _EQ036, GLOBAL( keyup),  VCC,  VCC,  VCC);
  _EQ036 = !adjsta0 &  adjsta1 &  adjsta2 & !mode;

-- Node name is 'seclset1' = 'seclow1' 
-- Equation name is 'seclset1', location is LC022, type is output.
 seclset1 = TFFE( _EQ037, GLOBAL( keyup),  VCC,  VCC,  VCC);
  _EQ037 = !adjsta0 &  adjsta1 &  adjsta2 & !mode &  seclset0;

-- Node name is 'seclset2' = 'seclow2' 
-- Equation name is 'seclset2', location is LC021, type is output.
 seclset2 = TFFE( _EQ038, GLOBAL( keyup),  VCC,  VCC,  VCC);
  _EQ038 = !adjsta0 &  adjsta1 &  adjsta2 & !mode &  seclset0 &  seclset1;

-- Node name is 'seclset3' = 'seclow3' 
-- Equation name is 'seclset3', location is LC030, type is output.
 seclset3 = TFFE( _EQ039, GLOBAL( keyup),  VCC,  VCC,  VCC);
  _EQ039 = !adjsta0 &  adjsta1 &  adjsta2 & !mode &  seclset0 &  seclset1 & 
              seclset2;

-- Node name is 'settime' = 'setmark' 
-- Equation name is 'settime', location is LC005, type is output.
 settime = TFFE( VCC,  begend,  VCC,  VCC,  VCC);

-- Node name is 'weekset0' = 'week0' 
-- Equation name is 'weekset0', location is LC045, type is output.
 weekset0 = TFFE( _EQ040, GLOBAL( keyup),  VCC,  VCC,  VCC);
  _EQ040 = !adjsta0 & !adjsta1 & !adjsta2 & !mode;

-- Node name is 'weekset1' = 'week1' 
-- Equation name is 'weekset1', location is LC028, type is output.
 weekset1 = TFFE( _EQ041, GLOBAL( keyup),  VCC,  VCC,  VCC);
  _EQ041 = !adjsta0 & !adjsta1 & !adjsta2 & !mode &  weekset0;

-- Node name is 'weekset2' = 'week2' 
-- Equation name is 'weekset2', location is LC027, type is output.
 weekset2 = TFFE( _EQ042, GLOBAL( keyup),  VCC,  VCC,  VCC);
  _EQ042 = !adjsta0 & !adjsta1 & !adjsta2 & !mode &  weekset0 &  weekset1;

-- Node name is 'weekset3' = 'week3' 
-- Equation name is 'weekset3', location is LC029, type is output.
 weekset3 = TFFE( _EQ043, GLOBAL( keyup),  VCC,  VCC,  VCC);
  _EQ043 = !adjsta0 & !adjsta1 & !adjsta2 & !mode &  weekset0 &  weekset1 & 
              weekset2;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                             c:\max2work\clock1\control.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 17,368K