📄 control.rpt
字号:
56 54 D FF + t 0 0 0 1 3 3 0 alarm_minlset0 (:86)
51 49 D FF + t 0 0 0 1 4 2 0 alarm_minlset1 (:85)
52 51 D FF + t 0 0 0 1 5 1 0 alarm_minlset2 (:84)
62 61 D FF + t 0 0 0 1 6 0 0 alarm_minlset3 (:83)
30 20 B FF + t 0 0 0 1 3 1 0 hourhset0 (:55)
49 46 C FF + t 0 0 0 1 4 0 0 hourhset1 (:54)
42 40 C FF + t 0 0 0 1 3 3 0 hourlset0 (:59)
44 41 C FF + t 0 0 0 1 4 2 0 hourlset1 (:58)
46 44 C FF + t 0 0 0 1 5 1 0 hourlset2 (:57)
39 36 C FF + t 0 0 0 1 6 0 0 hourlset3 (:56)
41 38 C FF + t 0 0 0 1 3 2 0 minhset0 (:62)
40 37 C FF + t 0 0 0 1 4 1 0 minhset1 (:61)
50 48 C FF + t 0 0 0 1 5 0 0 minhset2 (:60)
37 35 C FF + t 0 0 0 1 3 3 0 minlset0 (:66)
32 19 B FF + t 0 0 0 1 4 2 0 minlset1 (:65)
33 17 B FF + t 0 0 0 1 5 1 0 minlset2 (:64)
27 24 B FF + t 0 0 0 1 6 0 0 minlset3 (:63)
36 33 C FF + t 0 0 0 1 3 2 0 sechset0 (:69)
25 25 B FF + t 0 0 0 1 4 1 0 sechset1 (:68)
19 32 B FF + t 0 0 0 1 5 0 0 sechset2 (:67)
45 43 C FF + t 0 0 0 1 3 3 0 seclset0 (:73)
28 22 B FF + t 0 0 0 1 4 2 0 seclset1 (:72)
29 21 B FF + t 0 0 0 1 5 1 0 seclset2 (:71)
20 30 B FF + t 0 0 0 1 6 0 0 seclset3 (:70)
14 5 A FF t 0 0 0 1 0 0 0 settime (:43)
47 45 C FF + t 0 0 0 1 3 3 0 weekset0 (:53)
23 28 B FF + t 0 0 0 1 4 2 0 weekset1 (:52)
24 27 B FF + t 0 0 0 1 5 1 0 weekset2 (:51)
22 29 B FF + t 0 0 0 1 6 0 0 weekset3 (:50)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\max2work\clock1\control.rpt
control
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 39 C TFFE t 0 0 0 2 3 24 3 adjsta2 (:44)
- 42 C TFFE t 0 0 0 2 3 24 3 adjsta1 (:45)
- 34 C DFFE t 0 0 0 2 3 24 3 adjsta0 (:46)
- 55 D TFFE t 0 0 0 2 1 13 3 alarm_adjsta2 (:47)
- 50 D TFFE t 0 0 0 2 3 13 1 alarm_adjsta1 (:48)
- 58 D DFFE t 0 0 0 2 2 13 2 alarm_adjsta0 (:49)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\max2work\clock1\control.rpt
control
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+--- LC6 alarm_hourhset0
| +- LC5 settime
| |
| | Other LABs fed by signals
| | that feed LAB 'A'
LC | | | A B C D | Logic cells that feed LAB 'A':
Pin
15 -> - * | * - - - | <-- begend
67 -> - - | - - - - | <-- keyup
18 -> * - | * * * * | <-- mode
LC55 -> * - | * - - * | <-- alarm_adjsta2
LC50 -> * - | * - - * | <-- alarm_adjsta1
LC58 -> * - | * - - * | <-- alarm_adjsta0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\max2work\clock1\control.rpt
control
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----------------------- LC20 hourhset0
| +--------------------- LC19 minlset1
| | +------------------- LC17 minlset2
| | | +----------------- LC24 minlset3
| | | | +--------------- LC25 sechset1
| | | | | +------------- LC32 sechset2
| | | | | | +----------- LC22 seclset1
| | | | | | | +--------- LC21 seclset2
| | | | | | | | +------- LC30 seclset3
| | | | | | | | | +----- LC28 weekset1
| | | | | | | | | | +--- LC27 weekset2
| | | | | | | | | | | +- LC29 weekset3
| | | | | | | | | | | |
| | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'B':
LC19 -> - * * * - - - - - - - - | - * - - | <-- minlset1
LC17 -> - - * * - - - - - - - - | - * - - | <-- minlset2
LC25 -> - - - - * * - - - - - - | - * - - | <-- sechset1
LC22 -> - - - - - - * * * - - - | - * - - | <-- seclset1
LC21 -> - - - - - - - * * - - - | - * - - | <-- seclset2
LC28 -> - - - - - - - - - * * * | - * - - | <-- weekset1
LC27 -> - - - - - - - - - - * * | - * - - | <-- weekset2
Pin
67 -> - - - - - - - - - - - - | - - - - | <-- keyup
18 -> * * * * * * * * * * * * | * * * * | <-- mode
LC35 -> - * * * - - - - - - - - | - * - - | <-- minlset0
LC33 -> - - - - * * - - - - - - | - * - - | <-- sechset0
LC43 -> - - - - - - * * * - - - | - * - - | <-- seclset0
LC45 -> - - - - - - - - - * * * | - * - - | <-- weekset0
LC39 -> * * * * * * * * * * * * | - * * - | <-- adjsta2
LC42 -> * * * * * * * * * * * * | - * * - | <-- adjsta1
LC34 -> * * * * * * * * * * * * | - * * - | <-- adjsta0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\max2work\clock1\control.rpt
control
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+----------------------------- LC46 hourhset1
| +--------------------------- LC40 hourlset0
| | +------------------------- LC41 hourlset1
| | | +----------------------- LC44 hourlset2
| | | | +--------------------- LC36 hourlset3
| | | | | +------------------- LC38 minhset0
| | | | | | +----------------- LC37 minhset1
| | | | | | | +--------------- LC48 minhset2
| | | | | | | | +------------- LC35 minlset0
| | | | | | | | | +----------- LC33 sechset0
| | | | | | | | | | +--------- LC43 seclset0
| | | | | | | | | | | +------- LC45 weekset0
| | | | | | | | | | | | +----- LC39 adjsta2
| | | | | | | | | | | | | +--- LC42 adjsta1
| | | | | | | | | | | | | | +- LC34 adjsta0
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC40 -> - * * * * - - - - - - - - - - | - - * - | <-- hourlset0
LC41 -> - - * * * - - - - - - - - - - | - - * - | <-- hourlset1
LC44 -> - - - * * - - - - - - - - - - | - - * - | <-- hourlset2
LC38 -> - - - - - * * * - - - - - - - | - - * - | <-- minhset0
LC37 -> - - - - - - * * - - - - - - - | - - * - | <-- minhset1
LC39 -> * * * * * * * * * * * * * * * | - * * - | <-- adjsta2
LC42 -> * * * * * * * * * * * * * * * | - * * - | <-- adjsta1
LC34 -> * * * * * * * * * * * * * * * | - * * - | <-- adjsta0
Pin
17 -> - - - - - - - - - - - - * * * | - - * * | <-- enter
67 -> - - - - - - - - - - - - - - - | - - - - | <-- keyup
18 -> * * * * * * * * * * * * * * * | * * * * | <-- mode
LC20 -> * - - - - - - - - - - - - - - | - - * - | <-- hourhset0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\max2work\clock1\control.rpt
control
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+----------------------------- LC62 alarm_hourhset1
| +--------------------------- LC56 alarm_hourlset0
| | +------------------------- LC57 alarm_hourlset1
| | | +----------------------- LC59 alarm_hourlset2
| | | | +--------------------- LC60 alarm_hourlset3
| | | | | +------------------- LC52 alarm_minhset0
| | | | | | +----------------- LC53 alarm_minhset1
| | | | | | | +--------------- LC64 alarm_minhset2
| | | | | | | | +------------- LC54 alarm_minlset0
| | | | | | | | | +----------- LC49 alarm_minlset1
| | | | | | | | | | +--------- LC51 alarm_minlset2
| | | | | | | | | | | +------- LC61 alarm_minlset3
| | | | | | | | | | | | +----- LC55 alarm_adjsta2
| | | | | | | | | | | | | +--- LC50 alarm_adjsta1
| | | | | | | | | | | | | | +- LC58 alarm_adjsta0
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC56 -> - * * * * - - - - - - - - - - | - - - * | <-- alarm_hourlset0
LC57 -> - - * * * - - - - - - - - - - | - - - * | <-- alarm_hourlset1
LC59 -> - - - * * - - - - - - - - - - | - - - * | <-- alarm_hourlset2
LC52 -> - - - - - * * * - - - - - - - | - - - * | <-- alarm_minhset0
LC53 -> - - - - - - * * - - - - - - - | - - - * | <-- alarm_minhset1
LC54 -> - - - - - - - - * * * * - - - | - - - * | <-- alarm_minlset0
LC49 -> - - - - - - - - - * * * - - - | - - - * | <-- alarm_minlset1
LC51 -> - - - - - - - - - - * * - - - | - - - * | <-- alarm_minlset2
LC55 -> * * * * * * * * * * * * * * * | * - - * | <-- alarm_adjsta2
LC50 -> * * * * * * * * * * * * - * - | * - - * | <-- alarm_adjsta1
LC58 -> * * * * * * * * * * * * - * * | * - - * | <-- alarm_adjsta0
Pin
17 -> - - - - - - - - - - - - * * * | - - * * | <-- enter
67 -> - - - - - - - - - - - - - - - | - - - - | <-- keyup
18 -> * * * * * * * * * * * * * * * | * * * * | <-- mode
LC6 -> * - - - - - - - - - - - - - - | - - - * | <-- alarm_hourhset0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\max2work\clock1\control.rpt
control
** EQUATIONS **
begend : INPUT;
enter : INPUT;
keyup : INPUT;
mode : INPUT;
-- Node name is ':46' = 'adjsta0'
-- Equation name is 'adjsta0', location is LC034, type is buried.
adjsta0 = DFFE( _EQ001 $ VCC, enter, VCC, VCC, VCC);
_EQ001 = !adjsta0 & adjsta1 & adjsta2
# !adjsta0 & mode
# adjsta0 & !mode;
-- Node name is ':45' = 'adjsta1'
-- Equation name is 'adjsta1', location is LC042, type is buried.
adjsta1 = TFFE( _EQ002, enter, VCC, VCC, VCC);
_EQ002 = adjsta1 & adjsta2 & !mode
# adjsta0 & !mode;
-- Node name is ':44' = 'adjsta2'
-- Equation name is 'adjsta2', location is LC039, type is buried.
adjsta2 = TFFE( _EQ003, enter, VCC, VCC, VCC);
_EQ003 = adjsta0 & adjsta1 & !adjsta2 & !mode
# adjsta1 & adjsta2 & !mode;
-- Node name is ':49' = 'alarm_adjsta0'
-- Equation name is 'alarm_adjsta0', location is LC058, type is buried.
alarm_adjsta0 = DFFE( _EQ004 $ !mode, enter, VCC, VCC, VCC);
_EQ004 = !alarm_adjsta0 & !alarm_adjsta2 & mode
# !alarm_adjsta0 & !mode;
-- Node name is ':48' = 'alarm_adjsta1'
-- Equation name is 'alarm_adjsta1', location is LC050, type is buried.
alarm_adjsta1 = TFFE( _EQ005, enter, VCC, VCC, VCC);
_EQ005 = alarm_adjsta0 & !alarm_adjsta1 & !alarm_adjsta2 & mode
# alarm_adjsta0 & alarm_adjsta1 & mode
# alarm_adjsta1 & alarm_adjsta2 & mode;
-- Node name is ':47' = 'alarm_adjsta2'
-- Equation name is 'alarm_adjsta2', location is LC055, type is buried.
alarm_adjsta2 = TFFE( _EQ006, enter, VCC, VCC, VCC);
_EQ006 = alarm_adjsta2 & mode;
-- Node name is 'alarm_hourhset0' = 'alarm_hourhigh0'
-- Equation name is 'alarm_hourhset0', location is LC006, type is output.
alarm_hourhset0 = TFFE( _EQ007, GLOBAL( keyup), VCC, VCC, VCC);
_EQ007 = !alarm_adjsta0 & !alarm_adjsta1 & !alarm_adjsta2 & mode;
-- Node name is 'alarm_hourhset1' = 'alarm_hourhigh1'
-- Equation name is 'alarm_hourhset1', location is LC062, type is output.
alarm_hourhset1 = TFFE( _EQ008, GLOBAL( keyup), VCC, VCC, VCC);
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