📄 freq_clock.rpt
字号:
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: c:\max2work\clock0\freq_clock.rpt
freq_clock
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 6/ 96( 6%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\max2work\clock0\freq_clock.rpt
freq_clock
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 12 CLK
Device-Specific Information: c:\max2work\clock0\freq_clock.rpt
freq_clock
** EQUATIONS **
CLK : INPUT;
-- Node name is 'clock_clk'
-- Equation name is 'clock_clk', type is output
clock_clk = _LC6_B12;
-- Node name is ':14' = 'cnt0'
-- Equation name is 'cnt0', location is LC4_B9, type is buried.
cnt0 = DFFE(!cnt0, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is ':13' = 'cnt1'
-- Equation name is 'cnt1', location is LC6_B9, type is buried.
cnt1 = DFFE( _EQ001, GLOBAL( CLK), VCC, VCC, VCC);
_EQ001 = cnt0 & !cnt1
# !cnt0 & cnt1;
-- Node name is ':4' = 'cnt_1hz'
-- Equation name is 'cnt_1hz', location is LC1_B12, type is buried.
cnt_1hz = DFFE( _EQ002, GLOBAL( CLK), VCC, VCC, VCC);
_EQ002 = cnt_1hz & !_LC5_B9
# !cnt_1hz & _LC5_B9;
-- Node name is ':12' = 'cnt2'
-- Equation name is 'cnt2', location is LC7_B9, type is buried.
cnt2 = DFFE( _EQ003, GLOBAL( CLK), VCC, VCC, VCC);
_EQ003 = cnt0 & cnt1 & !cnt2
# cnt0 & cnt1 & _LC5_B9
# !cnt0 & cnt2 & !_LC5_B9
# !cnt1 & cnt2 & !_LC5_B9;
-- Node name is ':11' = 'cnt3'
-- Equation name is 'cnt3', location is LC3_B9, type is buried.
cnt3 = DFFE( _EQ004, GLOBAL( CLK), VCC, VCC, VCC);
_EQ004 = !cnt2 & cnt3
# !cnt0 & cnt3
# !cnt1 & cnt3
# cnt0 & cnt1 & cnt2 & !cnt3;
-- Node name is ':10' = 'cnt4'
-- Equation name is 'cnt4', location is LC1_B9, type is buried.
cnt4 = DFFE( _EQ005, GLOBAL( CLK), VCC, VCC, VCC);
_EQ005 = cnt4 & !_LC5_B9 & !_LC8_B9
# !cnt4 & _LC8_B9
# _LC5_B9 & _LC8_B9;
-- Node name is ':9' = 'cnt5'
-- Equation name is 'cnt5', location is LC5_B11, type is buried.
cnt5 = DFFE( _EQ006, GLOBAL( CLK), VCC, VCC, VCC);
_EQ006 = cnt5 & !_LC1_B11 & !_LC5_B9
# !cnt5 & _LC1_B11
# _LC1_B11 & _LC5_B9;
-- Node name is ':8' = 'cnt6'
-- Equation name is 'cnt6', location is LC3_B11, type is buried.
cnt6 = DFFE( _EQ007, GLOBAL( CLK), VCC, VCC, VCC);
_EQ007 = cnt5 & !cnt6 & _LC1_B11
# cnt5 & _LC1_B11 & _LC5_B9
# !cnt5 & cnt6 & !_LC5_B9
# cnt6 & !_LC1_B11 & !_LC5_B9;
-- Node name is ':7' = 'cnt7'
-- Equation name is 'cnt7', location is LC6_B11, type is buried.
cnt7 = DFFE( _EQ008, GLOBAL( CLK), VCC, VCC, VCC);
_EQ008 = cnt7 & !_LC4_B11 & !_LC5_B9
# !cnt7 & _LC4_B11
# _LC4_B11 & _LC5_B9;
-- Node name is ':6' = 'cnt8'
-- Equation name is 'cnt8', location is LC8_B11, type is buried.
cnt8 = DFFE( _EQ009, GLOBAL( CLK), VCC, VCC, VCC);
_EQ009 = cnt7 & !cnt8 & _LC4_B11
# cnt7 & _LC4_B11 & _LC5_B9
# !cnt7 & cnt8 & !_LC5_B9
# cnt8 & !_LC4_B11 & !_LC5_B9;
-- Node name is ':5' = 'cnt9'
-- Equation name is 'cnt9', location is LC7_B11, type is buried.
cnt9 = DFFE( _EQ010, GLOBAL( CLK), VCC, VCC, VCC);
_EQ010 = !cnt7 & cnt9
# cnt9 & !_LC4_B11
# !cnt8 & cnt9
# cnt7 & cnt8 & !cnt9 & _LC4_B11;
-- Node name is '|LPM_ADD_SUB:146|addcore:adder|:91' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B9', type is buried
_LC8_B9 = LCELL( _EQ011);
_EQ011 = cnt0 & cnt1 & cnt2 & cnt3;
-- Node name is '|LPM_ADD_SUB:146|addcore:adder|:95' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B11', type is buried
_LC1_B11 = LCELL( _EQ012);
_EQ012 = cnt4 & _LC8_B9;
-- Node name is '|LPM_ADD_SUB:146|addcore:adder|:103' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B11', type is buried
_LC4_B11 = LCELL( _EQ013);
_EQ013 = cnt5 & cnt6 & _LC1_B11;
-- Node name is ':2'
-- Equation name is '_LC6_B12', type is buried
_LC6_B12 = DFFE( _EQ014, GLOBAL( CLK), VCC, VCC, VCC);
_EQ014 = cnt_1hz & _LC5_B9
# !_LC5_B9 & _LC6_B12;
-- Node name is '~47~1'
-- Equation name is '~47~1', location is LC2_B11, type is buried.
-- synthesized logic cell
_LC2_B11 = LCELL( _EQ015);
_EQ015 = !cnt6
# !cnt7
# cnt9
# !cnt8;
-- Node name is '~47~2'
-- Equation name is '~47~2', location is LC2_B9, type is buried.
-- synthesized logic cell
_LC2_B9 = LCELL( _EQ016);
_EQ016 = _LC2_B11
# cnt3
# !cnt4
# !cnt5;
-- Node name is ':47'
-- Equation name is '_LC5_B9', type is buried
!_LC5_B9 = _LC5_B9~NOT;
_LC5_B9~NOT = LCELL( _EQ017);
_EQ017 = cnt0
# cnt1
# !cnt2
# _LC2_B9;
Project Information c:\max2work\clock0\freq_clock.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,924K
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