📄 control.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY control IS
PORT( mode: IN STD_LOGIC;
begend: IN STD_LOGIC; --key of begin&end
keyup: IN STD_LOGIC; --set time value
enter: IN STD_LOGIC; --enable the configuration of next time bit
settime: OUT STD_LOGIC;
weekset: OUT INTEGER RANGE 1 TO 8; --output to inform module "clock" to adjust time according to the newly-set time
hourhset: OUT INTEGER RANGE 0 TO 2; --HOUR high SET BY CONTROL PART
hourlset: OUT INTEGER RANGE 0 TO 9; --HOUR low SET BY CONTROL PART
minhset: OUT INTEGER RANGE 0 TO 5; --MINUTE high SET BY CONTROL PART
minlset: OUT INTEGER RANGE 0 TO 9; --MINUTE low SET BY CONTROL PART
sechset: OUT INTEGER RANGE 0 TO 5; --SECOND high SET BY CONTROL PART
seclset: OUT INTEGER RANGE 0 TO 9; --SECOND low SET BY CONTROL PART
alarm_hourhset: OUT INTEGER RANGE 0 TO 2; --alarm_HOUR high SET BY CONTROL PART
alarm_hourlset: OUT INTEGER RANGE 0 TO 9; --alarm_HOUR low SET BY CONTROL PART
alarm_minhset: OUT INTEGER RANGE 0 TO 5; --alarm_MINUTE high SET BY CONTROL PART
alarm_minlset: OUT INTEGER RANGE 0 TO 9); --alarm_MINUTE low SET BY CONTROL PART
END control;
ARCHITECTURE archi OF control IS
TYPE STATE IS(setweek,sethh,sethl,setmh,setml,setsh,setsl,ini); --eight operation states in the control part
TYPE alarm_STATE IS(sethh,sethl,setmh,setml,ini); --four operation states in the alarm_control part
SIGNAL adjsta: STATE;
SIGNAL alarm_adjsta: alarm_STATE;
SIGNAL setmark: STD_LOGIC;
SIGNAL seclow,minlow,hourlow: INTEGER RANGE 0 TO 9;
SIGNAL sechigh,minhigh: INTEGER RANGE 0 TO 5;
SIGNAL hourhigh: INTEGER RANGE 0 TO 2;
SIGNAL alarm_minlow,alarm_hourlow: INTEGER RANGE 0 TO 9;
SIGNAL alarm_minhigh: INTEGER RANGE 0 TO 5;
SIGNAL alarm_hourhigh: INTEGER RANGE 0 TO 2;
SIGNAL week: INTEGER RANGE 1 TO 8;
BEGIN
weekset<=week;
seclset<=seclow;
sechset<=sechigh;
minlset<=minlow;
minhset<=minhigh;
hourlset<=hourlow;
hourhset<=hourhigh;
alarm_minlset<=alarm_minlow;
alarm_minhset<=alarm_minhigh;
alarm_hourlset<=alarm_hourlow;
alarm_hourhset<=alarm_hourhigh;
settime<=setmark;
mark: --this process will decide the output control signal "settime" for "clock" module
PROCESS(begend)
begin
if begend'event and begend='1' then
if setmark='1' then
setmark<='0';
else
setmark<='1';
end if;
end if;
END PROCESS;
normal_run: --this process acts as core state machine
PROCESS(enter)
BEGIN
IF enter='1' AND enter'event THEN
if mode='0' then
case adjsta IS
WHEN ini=>
adjsta<=setweek;
WHEN setweek=>
adjsta<=sethh;
WHEN sethh=>
adjsta<=sethl;
WHEN sethl=>
adjsta<=setmh;
WHEN setmh=>
adjsta<=setml;
WHEN setml=>
adjsta<=setsh;
WHEN setsh=>
adjsta<=setsl;
WHEN setsl=>
adjsta<=setweek; --recycle
end case;
else
case alarm_adjsta IS
WHEN ini=>
alarm_adjsta<=sethh;
WHEN sethh=>
alarm_adjsta<=sethl;
WHEN sethl=>
alarm_adjsta<=setmh;
WHEN setmh=>
alarm_adjsta<=setml;
WHEN setml=>
alarm_adjsta<=sethh; --recycle
end case;
end if;
END IF;
END PROCESS;
time_adjust: --the set value increased as the "keyup" is pushed down
PROCESS(keyup)
BEGIN
if keyup='1' AND keyup'event THEN
if mode='0' then
case adjsta IS
WHEN setweek=>
week<=week+1;
WHEN sethh=>
hourhigh<=hourhigh+1;
WHEN sethl=>
hourlow<=hourlow+1;
WHEN setmh=>
minhigh<=minhigh+1;
WHEN setml=>
minlow<=minlow+1;
WHEN setsh=>
sechigh<=sechigh+1;
WHEN setsl=>
seclow<=seclow+1;
WHEN ini=>
NULL;
end case;
else
case alarm_adjsta IS
WHEN sethh=>
alarm_hourhigh<=alarm_hourhigh+1;
WHEN sethl=>
alarm_hourlow<=alarm_hourlow+1;
WHEN setmh=>
alarm_minhigh<=alarm_minhigh+1;
WHEN setml=>
alarm_minlow<=alarm_minlow+1;
WHEN ini=>
NULL;
end case;
end if;
end if;
END PROCESS;
END archi;
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