mux.vhd

vhdl实现时钟和闹钟功能

library ieee;
use ieee.std_logic_1164.all;
entity mux is
port(d0,d1,sel:in bit;
q:out bit);
end mux;
architecture con of mux is
begin
process(d0,d1,sel)
variable t1,t2,t3:bit;
begin
t1:= d0 and (not sel);
t2:=d1 and sel;
t3:=t1 or t2;
q<=t3;
end process;
end con;