📄 display.rpt
字号:
- 4 - C 20 OR2 0 4 0 1 :7042
- 4 - C 29 AND2 0 2 0 1 :7049
- 3 - C 29 OR2 0 4 0 1 :7050
- 1 - C 34 OR2 0 4 0 1 :7054
- 6 - C 33 OR2 2 2 0 1 :7061
- 5 - C 33 OR2 0 4 0 1 :7062
- 5 - D 20 AND2 0 1 0 1 :7084
- 8 - D 20 OR2 2 1 0 1 :7109
- 7 - D 20 OR2 1 2 0 1 :7111
- 6 - D 20 OR2 2 1 0 1 :7115
- 1 - D 34 AND2 s 1 3 0 2 ~7122~1
- 4 - D 34 AND2 0 2 1 0 :7122
- 4 - C 27 OR2 1 2 1 0 :7127
- 1 - C 27 AND2 1 1 0 1 :7128
- 1 - C 31 OR2 1 2 1 0 :7133
- 2 - C 31 OR2 1 3 1 0 :7145
- 5 - C 27 OR2 1 3 1 0 :7151
- 4 - F 18 OR2 s 4 0 0 1 ~7157~1
- 6 - F 18 OR2 s 0 4 0 1 ~7157~2
- 7 - F 12 OR2 s 4 0 0 1 ~7157~3
- 7 - F 18 OR2 s 0 4 0 1 ~7157~4
- 8 - F 18 OR2 s 0 4 0 1 ~7157~5
- 1 - F 10 AND2 s 2 0 0 1 ~7157~6
- 4 - F 11 OR2 s 0 4 0 1 ~7157~7
- 5 - F 11 OR2 s 4 0 0 1 ~7157~8
- 6 - F 11 OR2 s 0 4 0 1 ~7157~9
- 8 - F 11 OR2 s 0 4 0 1 ~7157~10
- 8 - C 28 AND2 s 2 0 0 1 ~7157~11
- 2 - C 28 OR2 s 0 4 0 1 ~7157~12
- 7 - C 23 OR2 s 4 0 0 1 ~7157~13
- 1 - C 23 OR2 s 0 3 0 1 ~7157~14
- 2 - C 25 OR2 s 0 4 0 1 ~7157~15
- 3 - C 25 OR2 s 1 2 0 1 ~7157~16
- 6 - C 32 OR2 s 4 0 0 1 ~7157~17
- 7 - C 32 OR2 s 0 4 0 1 ~7157~18
- 7 - C 20 AND2 s 2 0 0 1 ~7157~19
- 1 - C 20 OR2 s 0 4 0 1 ~7157~20
- 4 - C 36 OR2 s 4 0 0 1 ~7157~21
- 4 - C 25 OR2 s 0 4 0 1 ~7157~22
- 5 - C 25 OR2 s 0 4 0 1 ~7157~23
- 6 - C 25 AND2 s 1 2 0 1 ~7157~24
- 1 - C 25 OR2 1 3 1 0 :7157
- 6 - C 22 OR2 1 3 1 0 :7163
- 7 - C 35 OR2 1 3 1 0 :7169
- 6 - C 29 OR2 1 3 1 0 :7175
- 3 - C 33 OR2 1 3 1 0 :7181
- 5 - D 34 OR2 2 1 0 1 :7187
- 2 - D 34 OR2 0 4 0 1 :7188
- 2 - D 20 OR2 2 1 0 1 :7193
- 3 - D 33 OR2 1 3 0 1 :7194
- 7 - D 34 OR2 2 1 0 1 :7199
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information:d:\progra~1\maxplus2\maxplusworks\clock1\display.rpt
display
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 37/144( 25%) 0/ 72( 0%) 45/ 72( 62%) 7/16( 43%) 4/16( 25%) 0/16( 0%)
D: 12/144( 8%) 0/ 72( 0%) 1/ 72( 1%) 1/16( 6%) 2/16( 12%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 27/144( 18%) 31/ 72( 43%) 0/ 72( 0%) 10/16( 62%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
26: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
27: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
29: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
30: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
31: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
32: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
33: 7/24( 29%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
36: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:d:\progra~1\maxplus2\maxplusworks\clock1\display.rpt
display
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 5 SCLK
Device-Specific Information:d:\progra~1\maxplus2\maxplusworks\clock1\display.rpt
display
** EQUATIONS **
alarm_hourhdis0 : INPUT;
alarm_hourhdis1 : INPUT;
alarm_hourldis0 : INPUT;
alarm_hourldis1 : INPUT;
alarm_hourldis2 : INPUT;
alarm_hourldis3 : INPUT;
alarm_minhdis0 : INPUT;
alarm_minhdis1 : INPUT;
alarm_minhdis2 : INPUT;
alarm_minldis0 : INPUT;
alarm_minldis1 : INPUT;
alarm_minldis2 : INPUT;
alarm_minldis3 : INPUT;
hourhdis0 : INPUT;
hourhdis1 : INPUT;
hourldis0 : INPUT;
hourldis1 : INPUT;
hourldis2 : INPUT;
hourldis3 : INPUT;
minhdis0 : INPUT;
minhdis1 : INPUT;
minhdis2 : INPUT;
minldis0 : INPUT;
minldis1 : INPUT;
minldis2 : INPUT;
minldis3 : INPUT;
mode : INPUT;
RESET : INPUT;
SCLK : INPUT;
sechdis0 : INPUT;
sechdis1 : INPUT;
sechdis2 : INPUT;
secldis0 : INPUT;
secldis1 : INPUT;
secldis2 : INPUT;
secldis3 : INPUT;
weekdis0 : INPUT;
weekdis1 : INPUT;
weekdis2 : INPUT;
weekdis3 : INPUT;
-- Node name is 'ADDSEL0'
-- Equation name is 'ADDSEL0', type is output
ADDSEL0 = _LC1_C31;
-- Node name is 'ADDSEL1'
-- Equation name is 'ADDSEL1', type is output
ADDSEL1 = _LC4_C27;
-- Node name is 'ADDSEL2'
-- Equation name is 'ADDSEL2', type is output
ADDSEL2 = _LC4_D34;
-- Node name is ':61' = 'alarm_CURSTA0'
-- Equation name is 'alarm_CURSTA0', location is LC4_D20, type is buried.
alarm_CURSTA0 = DFFE( _LC6_D20, GLOBAL( SCLK), VCC, VCC, !_LC1_D20);
-- Node name is ':60' = 'alarm_CURSTA1'
-- Equation name is 'alarm_CURSTA1', location is LC3_D20, type is buried.
alarm_CURSTA1 = DFFE( _LC8_D20, GLOBAL( SCLK), VCC, VCC, !_LC1_D20);
-- Node name is ':59' = 'CURSTA0'
-- Equation name is 'CURSTA0', location is LC3_D34, type is buried.
CURSTA0 = DFFE( _LC7_D34, GLOBAL( SCLK), VCC, VCC, !_LC1_D20);
-- Node name is ':58' = 'CURSTA1'
-- Equation name is 'CURSTA1', location is LC7_D33, type is buried.
CURSTA1 = DFFE( _LC2_D20, GLOBAL( SCLK), VCC, VCC, !_LC1_D20);
-- Node name is ':57' = 'CURSTA2'
-- Equation name is 'CURSTA2', location is LC6_D34, type is buried.
CURSTA2 = DFFE( _LC5_D34, GLOBAL( SCLK), VCC, VCC, !_LC1_D20);
-- Node name is 'RESET~1'
-- Equation name is 'RESET~1', location is LC1_D20, type is buried.
-- synthesized logic cell
!_LC1_D20 = _LC1_D20~NOT;
_LC1_D20~NOT = LCELL(!RESET);
-- Node name is 'SECDIS0'
-- Equation name is 'SECDIS0', type is output
SECDIS0 = _LC3_C33;
-- Node name is 'SECDIS1'
-- Equation name is 'SECDIS1', type is output
SECDIS1 = _LC6_C29;
-- Node name is 'SECDIS2'
-- Equation name is 'SECDIS2', type is output
SECDIS2 = _LC7_C35;
-- Node name is 'SECDIS3'
-- Equation name is 'SECDIS3', type is output
SECDIS3 = _LC6_C22;
-- Node name is 'SECDIS4'
-- Equation name is 'SECDIS4', type is output
SECDIS4 = _LC1_C25;
-- Node name is 'SECDIS5'
-- Equation name is 'SECDIS5', type is output
SECDIS5 = _LC5_C27;
-- Node name is 'SECDIS6'
-- Equation name is 'SECDIS6', type is output
SECDIS6 = _LC2_C31;
-- Node name is 'SECDIS7'
-- Equation name is 'SECDIS7', type is output
SECDIS7 = GND;
-- Node name is ':1832'
-- Equation name is '_LC8_C23', type is buried
!_LC8_C23 = _LC8_C23~NOT;
_LC8_C23~NOT = LCELL( _EQ001);
_EQ001 = hourldis3
# hourldis0
# !hourldis1
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