📄 display.rpt
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Device-Specific Information:d:\progra~1\maxplus2\maxplusworks\clock1\display.rpt
display
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
58 - - - 31 INPUT ^ 0 0 0 5 alarm_hourhdis0
133 - - C -- INPUT ^ 0 0 0 5 alarm_hourhdis1
64 - - - 26 INPUT ^ 0 0 0 9 alarm_hourldis0
190 - - - 22 INPUT ^ 0 0 0 10 alarm_hourldis1
62 - - - 28 INPUT ^ 0 0 0 10 alarm_hourldis2
186 - - - 19 INPUT ^ 0 0 0 10 alarm_hourldis3
69 - - - 23 INPUT ^ 0 0 0 8 alarm_minhdis0
203 - - - 32 INPUT ^ 0 0 0 8 alarm_minhdis1
131 - - C -- INPUT ^ 0 0 0 7 alarm_minhdis2
65 - - - 26 INPUT ^ 0 0 0 8 alarm_minldis0
61 - - - 29 INPUT ^ 0 0 0 9 alarm_minldis1
208 - - - 36 INPUT ^ 0 0 0 9 alarm_minldis2
135 - - C -- INPUT ^ 0 0 0 9 alarm_minldis3
80 - - - -- INPUT ^ 0 0 0 5 hourhdis0
182 - - - -- INPUT ^ 0 0 0 5 hourhdis1
132 - - C -- INPUT ^ 0 0 0 8 hourldis0
24 - - C -- INPUT ^ 0 0 0 9 hourldis1
191 - - - 23 INPUT ^ 0 0 0 9 hourldis2
134 - - C -- INPUT ^ 0 0 0 9 hourldis3
136 - - C -- INPUT ^ 0 0 0 8 minhdis0
207 - - - 35 INPUT ^ 0 0 0 8 minhdis1
73 - - - 20 INPUT ^ 0 0 0 7 minhdis2
183 - - - -- INPUT ^ 0 0 0 8 minldis0
111 - - F -- INPUT ^ 0 0 0 9 minldis1
161 - - - 04 INPUT ^ 0 0 0 9 minldis2
184 - - - -- INPUT ^ 0 0 0 9 minldis3
78 - - - -- INPUT ^ 0 0 0 18 mode
25 - - D -- INPUT ^ 0 0 0 6 RESET
79 - - - -- INPUT G ^ 0 0 0 0 SCLK
112 - - F -- INPUT ^ 0 0 0 8 sechdis0
177 - - - 16 INPUT ^ 0 0 0 9 sechdis1
44 - - F -- INPUT ^ 0 0 0 8 sechdis2
45 - - F -- INPUT ^ 0 0 0 9 secldis0
113 - - F -- INPUT ^ 0 0 0 10 secldis1
114 - - F -- INPUT ^ 0 0 0 10 secldis2
103 - - - 02 INPUT ^ 0 0 0 10 secldis3
47 - - F -- INPUT ^ 0 0 0 8 weekdis0
115 - - F -- INPUT ^ 0 0 0 9 weekdis1
46 - - F -- INPUT ^ 0 0 0 9 weekdis2
116 - - F -- INPUT ^ 0 0 0 9 weekdis3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information:d:\progra~1\maxplus2\maxplusworks\clock1\display.rpt
display
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
16 - - C -- OUTPUT 0 1 0 0 ADDSEL0
19 - - C -- OUTPUT 0 1 0 0 ADDSEL1
28 - - D -- OUTPUT 0 1 0 0 ADDSEL2
18 - - C -- OUTPUT 0 1 0 0 SECDIS0
200 - - - 30 OUTPUT 0 1 0 0 SECDIS1
54 - - - 35 OUTPUT 0 1 0 0 SECDIS2
71 - - - 21 OUTPUT 0 1 0 0 SECDIS3
67 - - - 25 OUTPUT 0 1 0 0 SECDIS4
198 - - - 28 OUTPUT 0 1 0 0 SECDIS5
17 - - C -- OUTPUT 0 1 0 0 SECDIS6
128 - - D -- OUTPUT 0 0 0 0 SECDIS7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:d:\progra~1\maxplus2\maxplusworks\clock1\display.rpt
display
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - D 20 SOFT s ! 1 0 0 5 RESET~1
- 6 - D 34 DFFE + 0 2 0 7 CURSTA2 (:57)
- 7 - D 33 DFFE + 0 2 0 8 CURSTA1 (:58)
- 3 - D 34 DFFE + 0 2 0 7 CURSTA0 (:59)
- 3 - D 20 DFFE + 0 2 0 17 alarm_CURSTA1 (:60)
- 4 - D 20 DFFE + 0 2 0 18 alarm_CURSTA0 (:61)
- 8 - C 23 OR2 ! 4 0 0 2 :1832
- 4 - C 23 OR2 ! 4 0 0 2 :1844
- 5 - C 23 AND2 4 0 0 6 :1856
- 5 - C 30 OR2 0 3 0 1 :1919
- 3 - C 23 OR2 4 0 0 1 :1972
- 2 - C 23 OR2 0 3 0 1 :1981
- 1 - C 19 OR2 4 0 0 1 :2029
- 3 - C 19 AND2 s 3 0 0 3 ~2039~1
- 2 - C 19 OR2 0 4 0 1 :2039
- 6 - C 19 OR2 4 0 0 2 :2071
- 1 - C 28 AND2 3 0 0 5 :2345
- 3 - C 30 OR2 3 0 0 1 :2410
- 6 - C 28 OR2 3 0 0 1 :2470
- 5 - C 28 OR2 3 0 0 1 :2560
- 6 - F 17 OR2 ! 4 0 0 2 :2830
- 2 - F 16 OR2 ! 4 0 0 2 :2842
- 3 - F 17 AND2 4 0 0 6 :2854
- 6 - F 07 OR2 0 3 0 1 :2917
- 6 - F 16 OR2 4 0 0 1 :2970
- 7 - F 16 OR2 0 4 0 1 :2977
- 5 - F 17 OR2 4 0 0 1 :3027
- 8 - F 17 AND2 s 3 0 0 3 ~3037~1
- 1 - F 17 OR2 0 4 0 1 :3037
- 2 - F 17 OR2 4 0 0 2 :3069
- 6 - F 06 OR2 ! 3 0 0 1 :3323
- 7 - F 06 OR2 ! 3 0 0 2 :3333
- 4 - F 06 AND2 3 0 0 5 :3343
- 8 - F 06 OR2 3 1 0 1 :3460
- 2 - F 06 AND2 s 2 0 0 3 ~3526~1
- 5 - F 06 OR2 s 3 1 0 1 ~3526~2
- 3 - F 06 OR2 3 0 0 2 :3558
- 6 - F 13 OR2 ! 4 0 0 2 :3828
- 5 - F 13 OR2 ! 4 0 0 2 :3840
- 2 - F 13 AND2 4 0 0 4 :3852
- 8 - F 13 OR2 4 0 0 1 :3915
- 4 - F 13 OR2 4 0 0 1 :3968
- 4 - F 16 OR2 0 4 0 1 :3975
- 1 - F 13 OR2 4 0 0 1 :4025
- 2 - F 18 AND2 s 3 0 0 2 ~4035~1
- 6 - F 14 OR2 0 4 0 1 :4035
- 3 - F 14 OR2 0 2 0 1 :4065
- 3 - F 13 OR2 4 0 0 2 :4067
- 6 - F 12 OR2 ! 4 0 0 2 :4337
- 4 - F 12 OR2 ! 4 0 0 2 :4349
- 1 - F 12 AND2 4 0 0 6 :4361
- 3 - F 07 OR2 0 3 0 1 :4424
- 5 - F 12 OR2 4 0 0 1 :4477
- 5 - F 18 OR2 0 4 0 1 :4484
- 3 - F 12 OR2 4 0 0 1 :4534
- 3 - F 18 AND2 s 3 0 0 3 ~4544~1
- 1 - F 18 OR2 s 0 3 0 1 ~4544~2
- 2 - F 12 OR2 4 0 0 2 :4576
- 4 - D 33 AND2 0 3 0 8 :4601
- 6 - D 33 AND2 0 3 0 12 :4611
- 5 - D 33 AND2 0 3 0 9 :4621
- 2 - D 33 OR2 ! 0 3 0 11 :4631
- 8 - D 33 OR2 ! 0 3 0 9 :4641
- 1 - D 33 OR2 ! 0 3 0 9 :4651
- 7 - F 07 OR2 0 4 0 1 :4723
- 7 - F 13 OR2 s 4 0 0 1 ~4724~1
- 8 - F 12 OR2 s 4 0 0 2 ~4725~1
- 8 - F 07 OR2 0 4 0 1 :4726
- 1 - F 06 OR2 s 3 0 0 2 ~4727~1
- 4 - F 07 OR2 0 4 0 1 :4729
- 4 - F 17 OR2 s 4 0 0 2 ~4730~1
- 2 - C 30 OR2 0 4 0 1 :4732
- 6 - C 30 OR2 s 3 0 0 1 ~4733~1
- 4 - C 31 OR2 0 4 0 1 :4735
- 6 - C 23 OR2 s 4 0 0 2 ~4736~1
- 5 - C 31 OR2 1 2 0 1 :4738
- 1 - F 07 OR2 0 4 0 1 :4748
- 5 - F 07 OR2 0 4 0 1 :4749
- 2 - F 07 OR2 0 4 0 1 :4750
- 4 - C 30 OR2 0 4 0 1 :4753
- 1 - C 30 OR2 0 3 0 1 :4756
- 2 - C 22 OR2 2 2 0 1 :4759
- 3 - F 16 OR2 0 4 0 1 :4790
- 5 - F 16 OR2 0 4 0 1 :4791
- 8 - F 16 OR2 0 4 0 1 :4792
- 1 - F 16 OR2 0 4 0 1 :4795
- 1 - C 22 OR2 0 4 0 1 :4798
- 3 - C 22 OR2 2 2 0 1 :4801
- 1 - F 11 OR2 0 3 0 1 :4807
- 3 - F 11 OR2 0 3 0 1 :4810
- 3 - C 28 OR2 3 1 0 1 :4817
- 2 - F 11 OR2 0 4 0 1 :4818
- 3 - C 35 OR2 0 4 0 1 :4819
- 4 - C 35 OR2 2 2 0 1 :4822
- 7 - F 14 OR2 0 4 0 1 :4828
- 8 - F 14 OR2 0 4 0 1 :4831
- 4 - C 28 OR2 3 1 0 1 :4838
- 2 - F 14 OR2 0 4 0 1 :4839
- 8 - C 19 OR2 0 4 0 1 :4840
- 1 - C 29 OR2 0 2 0 1 :4843
- 4 - F 14 OR2 0 4 0 1 :4849
- 5 - F 14 OR2 0 4 0 1 :4852
- 1 - F 14 OR2 0 4 0 1 :4855
- 7 - C 28 OR2 0 4 0 1 :4858
- 1 - C 33 OR2 0 4 0 1 :4861
- 2 - C 33 OR2 2 2 0 1 :4864
- 8 - D 34 OR2 0 4 0 2 :4927
- 5 - C 36 OR2 ! 4 0 0 2 :5667
- 2 - C 36 OR2 ! 4 0 0 2 :5679
- 7 - C 36 AND2 4 0 0 4 :5691
- 1 - C 36 OR2 4 0 0 1 :5754
- 3 - C 36 OR2 4 0 0 1 :5807
- 5 - C 22 OR2 0 4 0 1 :5814
- 6 - C 36 OR2 4 0 0 1 :5864
- 3 - C 31 AND2 s 3 0 0 2 ~5874~1
- 2 - C 29 OR2 0 4 0 1 :5874
- 4 - C 33 OR2 0 2 0 1 :5904
- 8 - C 36 OR2 4 0 0 2 :5906
- 8 - C 26 OR2 ! 3 0 0 1 :6158
- 2 - C 20 AND2 3 0 0 4 :6178
- 2 - C 26 OR2 3 0 0 1 :6243
- 3 - C 20 OR2 3 0 0 1 :6303
- 6 - C 20 OR2 s 3 0 0 1 ~6361~1
- 5 - C 20 OR2 3 0 0 2 :6393
- 5 - C 32 OR2 ! 4 0 0 2 :6661
- 2 - C 32 OR2 ! 4 0 0 2 :6673
- 8 - C 32 AND2 4 0 0 6 :6685
- 4 - C 26 OR2 0 3 0 1 :6748
- 1 - C 32 OR2 4 0 0 1 :6801
- 3 - C 32 OR2 0 4 0 1 :6808
- 6 - C 34 OR2 4 0 0 1 :6858
- 2 - C 34 AND2 s 3 0 0 3 ~6868~1
- 4 - C 34 OR2 0 4 0 1 :6868
- 5 - C 34 OR2 0 2 0 1 :6898
- 3 - C 34 OR2 4 0 0 2 :6900
- 8 - C 22 OR2 ! 0 2 0 7 :6921
- 3 - C 26 OR2 0 4 0 1 :6982
- 6 - C 26 OR2 s 3 0 0 1 ~6983~1
- 4 - C 32 OR2 s 4 0 0 2 ~6984~1
- 6 - C 31 OR2 s 4 0 0 1 ~6986~1
- 8 - C 31 AND2 1 2 0 1 :6989
- 7 - C 31 OR2 0 4 0 1 :6990
- 5 - C 26 OR2 0 4 0 1 :6994
- 1 - C 35 AND2 2 2 0 1 :7001
- 1 - C 26 OR2 0 4 0 1 :7002
- 4 - C 22 OR2 0 4 0 1 :7018
- 2 - C 35 OR2 2 2 0 1 :7025
- 7 - C 22 OR2 0 4 0 1 :7026
- 5 - C 35 OR2 0 3 0 1 :7030
- 8 - C 35 OR2 2 2 0 1 :7037
- 6 - C 35 OR2 0 4 0 1 :7038
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