ring.vhd

来自「vhdl实现时钟和闹钟功能」· VHDL 代码 · 共 44 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY ring IS
 PORT(RESET:      IN STD_LOGIC;
      alarm_switch:     IN STD_LOGIC;
      freq_h:     IN STD_LOGIC;
      freq_l:     IN STD_LOGIC;
      ALARM:      OUT STD_LOGIC;                         --dirve signal for the bell
      hourhdis:   IN INTEGER RANGE 0 TO 2;               --time information recieved from module of "clock"
      hourldis:   IN INTEGER RANGE 0 TO 9;
      minhdis:    IN INTEGER RANGE 0 TO 5;
      minldis:    IN INTEGER RANGE 0 TO 9;
      sechdis:    IN INTEGER RANGE 0 TO 5;
      secldis:    IN INTEGER RANGE 0 TO 9;
      alarm_hourhdis:   IN INTEGER RANGE 0 TO 2;         --alarm's time information recieved from module of "clock"
      alarm_hourldis:   IN INTEGER RANGE 0 TO 9;
      alarm_minhdis:    IN INTEGER RANGE 0 TO 5;
      alarm_minldis:    IN INTEGER RANGE 0 TO 9);
 END ring;
ARCHITECTURE archi OF ring IS
   BEGIN
   PROCESS(secldis,alarm_switch)
    BEGIN                              --the clock alarm
    IF reset='1' THEN
          ALARM<='0';
    ELSIF (minhdis=5 and minldis=9 and sechdis=5 and secldis=0) OR
          (minhdis=5 and minldis=9 and sechdis=5 and secldis=2) OR
          (minhdis=5 and minldis=9 and sechdis=5 and secldis=4) OR
          (minhdis=5 and minldis=9 and sechdis=5 and secldis=6) OR
          (minhdis=5 and minldis=9 and sechdis=5 and secldis=8) THEN
            ALARM<=freq_l;
    ELSIF (minhdis=0 and minldis=0 and sechdis=0 and secldis=0) OR
          (alarm_hourhdis=hourhdis and alarm_hourldis=hourldis and
           alarm_minhdis=minhdis and alarm_minldis=minLdis and alarm_switch='1')
    THEN
            ALARM<=freq_h;
    ELSE  ALARM<='0';
    END IF;
 END PROCESS;
END archi;