freq_dou.vhd

来自「vhdl实现时钟和闹钟功能」· VHDL 代码 · 共 28 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY freq_dou IS
PORT(clk:IN STD_LOGIC;
     dou_clk:OUT STD_LOGIC);
END freq_dou;

ARCHITECTURE freq_arc OF freq_dou IS
  SIGNAL cnt_10hz:STD_LOGIC;
BEGIN
PROCESS(CLK)
VARIABLE cnt:INTEGER RANGE 0 TO 128;
CONSTANT modu_10hz:INTEGER:=50;
BEGIN
IF(CLK'EVENT AND CLK='1') THEN
  IF cnt=modu_10hz THEN
    cnt:=0;
    cnt_10hz<= NOT cnt_10hz;
    dou_clk<=cnt_10hz;
  END IF;
  cnt:=cnt+1;
END IF;
END PROCESS;
END freq_arc;