📄 alarm_clock.rpt
字号:
B9 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 10/22( 45%)
B10 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
B11 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 10/22( 45%)
B12 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 5/22( 22%)
B13 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 14/22( 63%)
B14 8/ 8(100%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 20/22( 90%)
B15 8/ 8(100%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 18/22( 81%)
B16 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 1/2 9/22( 40%)
B17 6/ 8( 75%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 16/22( 72%)
B18 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 17/22( 77%)
B20 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 0/2 0/2 4/22( 18%)
B21 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 11/22( 50%)
B22 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 5/22( 22%)
B23 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 1/2 1/2 6/22( 27%)
B24 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 1/2 0/2 2/22( 9%)
B25 6/ 8( 75%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 13/22( 59%)
B26 3/ 8( 37%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 6/22( 27%)
B27 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 12/22( 54%)
B28 8/ 8(100%) 3/ 8( 37%) 1/ 8( 12%) 0/2 0/2 16/22( 72%)
B29 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 1/2 6/22( 27%)
B30 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 12/22( 54%)
B31 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 2/2 1/2 6/22( 27%)
B32 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 17/22( 77%)
B33 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 18/22( 81%)
B34 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 1/2 8/22( 36%)
B35 7/ 8( 87%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 8/22( 36%)
B36 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 1/22( 4%)
D15 7/ 8( 87%) 2/ 8( 25%) 0/ 8( 0%) 2/2 0/2 3/22( 13%)
D19 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
D23 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 1/2 0/2 5/22( 22%)
D24 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 5/22( 22%)
D29 3/ 8( 37%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 2/22( 9%)
F4 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 11/22( 50%)
F9 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 3/22( 13%)
F14 7/ 8( 87%) 3/ 8( 37%) 2/ 8( 25%) 0/2 0/2 14/22( 63%)
F15 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 4/22( 18%)
F16 8/ 8(100%) 2/ 8( 25%) 8/ 8(100%) 1/2 0/2 4/22( 18%)
F18 7/ 8( 87%) 5/ 8( 62%) 6/ 8( 75%) 1/2 0/2 2/22( 9%)
F20 8/ 8(100%) 6/ 8( 75%) 5/ 8( 62%) 1/2 0/2 9/22( 40%)
F26 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 1/2 0/2 14/22( 63%)
F28 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 4/22( 18%)
F31 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 2/2 0/2 3/22( 13%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 0/6 ( 0%)
Total I/O pins used: 20/141 ( 14%)
Total logic cells used: 374/1728 ( 21%)
Total embedded cells used: 0/96 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.39/4 ( 84%)
Total fan-in: 1270/6912 ( 18%)
Total input pins required: 8
Total input I/O cell registers required: 0
Total output pins required: 12
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 374
Total flipflops required: 105
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 86/1728 ( 4%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 8 0 0 0 0 1 0 0 8 0 0 0 0 0 25/0
B: 7 7 8 7 7 8 8 0 8 1 8 8 8 8 8 8 6 8 0 0 8 8 8 8 8 6 3 7 8 8 8 8 8 8 8 7 2 244/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 0 0 1 0 0 0 8 8 0 0 0 0 3 0 0 0 0 0 0 0 27/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 8 0 0 0 0 8 0 0 0 0 7 8 8 0 7 0 0 8 0 0 0 0 0 8 0 8 0 0 8 0 0 0 0 0 78/0
Total: 7 7 8 15 7 8 8 0 16 1 8 8 8 15 23 16 6 15 0 9 16 8 8 24 16 6 11 7 17 11 8 24 8 8 8 7 2 374/0
Device-Specific Information: c:\max2work\clock1\alarm_clock.rpt
alarm_clock
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
93 - - - 10 INPUT ^ 0 0 0 1 alarm_switch
92 - - - 11 INPUT ^ 0 0 0 1 begend
9 - - A -- INPUT ^ 0 0 0 32 clk_1khz
89 - - - 13 INPUT ^ 0 0 0 1 enter
87 - - - 14 INPUT ^ 0 0 0 1 keyup
90 - - - 12 INPUT ^ 0 0 0 36 mode
85 - - - 16 INPUT ^ 0 0 0 7 reset
75 - - - 19 INPUT ^ 0 0 0 1 sel
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\max2work\clock1\alarm_clock.rpt
alarm_clock
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
197 - - - 28 OUTPUT 0 1 0 0 addsel0
195 - - - 26 OUTPUT 0 1 0 0 addsel1
192 - - - 24 OUTPUT 0 1 0 0 addsel2
38 - - E -- OUTPUT 0 1 0 0 alarm
187 - - - 20 OUTPUT 0 1 0 0 secdis0
177 - - - 16 OUTPUT 0 1 0 0 secdis1
175 - - - 14 OUTPUT 0 1 0 0 secdis2
173 - - - 13 OUTPUT 0 1 0 0 secdis3
198 - - - 28 OUTPUT 0 1 0 0 secdis4
196 - - - 27 OUTPUT 0 1 0 0 secdis5
193 - - - 25 OUTPUT 0 1 0 0 secdis6
191 - - - 23 OUTPUT 0 0 0 0 secdis7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\max2work\clock1\alarm_clock.rpt
alarm_clock
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - B 21 OR2 ! 0 2 0 1 |CLOCK:1|LPM_ADD_SUB:447|addcore:adder|:59
- 5 - B 06 OR2 ! 0 3 0 1 |CLOCK:1|LPM_ADD_SUB:532|addcore:adder|:63
- 2 - B 18 AND2 0 2 0 4 |CLOCK:1|LPM_ADD_SUB:798|addcore:adder|:59
- 4 - B 09 AND2 0 2 0 1 |CLOCK:1|LPM_ADD_SUB:798|addcore:adder|:63
- 7 - B 20 OR2 ! 0 2 0 1 |CLOCK:1|LPM_ADD_SUB:952|addcore:adder|:55
- 2 - B 25 AND2 0 2 0 1 |CLOCK:1|LPM_ADD_SUB:1129|addcore:adder|:59
- 3 - B 23 AND2 0 3 0 2 |CLOCK:1|LPM_ADD_SUB:1129|addcore:adder|:63
- 8 - B 23 DFFE 0 5 0 11 |CLOCK:1|seclow3 (|CLOCK:1|:51)
- 5 - B 29 DFFE 0 5 0 11 |CLOCK:1|seclow2 (|CLOCK:1|:52)
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