📄 alarm_clock.rpt
字号:
|control:2|lpm_add_sub:1491|altshift:result_ext_latency_ffs|
|control:2|lpm_add_sub:1491|altshift:carry_ext_latency_ffs|
|control:2|lpm_add_sub:1491|altshift:oflow_ext_latency_ffs|
|display:3|
|ring:4|
|mux:5|
|dou:6|
|dou:7|
|dou:25|
|freq_clock:20|
|freq_clock:20|lpm_add_sub:146|
|freq_clock:20|lpm_add_sub:146|addcore:adder|
|freq_clock:20|lpm_add_sub:146|altshift:result_ext_latency_ffs|
|freq_clock:20|lpm_add_sub:146|altshift:carry_ext_latency_ffs|
|freq_clock:20|lpm_add_sub:146|altshift:oflow_ext_latency_ffs|
|freq_dou:21|
|freq_dou:21|lpm_add_sub:124|
|freq_dou:21|lpm_add_sub:124|addcore:adder|
|freq_dou:21|lpm_add_sub:124|altshift:result_ext_latency_ffs|
|freq_dou:21|lpm_add_sub:124|altshift:carry_ext_latency_ffs|
|freq_dou:21|lpm_add_sub:124|altshift:oflow_ext_latency_ffs|
|freq_ringl:22|
|freq_ringl:22|lpm_add_sub:58|
|freq_ringl:22|lpm_add_sub:58|addcore:adder|
|freq_ringl:22|lpm_add_sub:58|altshift:result_ext_latency_ffs|
|freq_ringl:22|lpm_add_sub:58|altshift:carry_ext_latency_ffs|
|freq_ringl:22|lpm_add_sub:58|altshift:oflow_ext_latency_ffs|
Device-Specific Information: c:\max2work\clock1\alarm_clock.rpt
alarm_clock
***** Logic for device 'alarm_clock' compiled without errors.
Device: EP1K30QC208-3
ACEX 1K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R
E E E E E E E E E s a s a s a s E E s E E E s E s E s E E E E E E E E E E E E E E
S S S S S S S V S S e d e d e d e S S e S V S S e S e S e S S S S S S S S S S S S S S
E E E E E E E C E E c d c d V c d c E E c E C E E V c E c E c E E E E E E V E E E E E E E E
R R R R R R R C R R d s d s C d s d R R d R C R R C d R d R d R R R R R R C R R R R R R R R
V V V V V V V I V V i e i e C i e i V V G i V I G G G G V V C i V i V i V G V V V V V C V V V V V V V V
E E E E E E E N E E s l s l I s l s E E N s E N N N N N E E I s E s E s E N E E E E E I E E E E E E E E
D D D D D D D T D D 4 0 5 1 O 6 2 7 D D D 0 D T D D D D D D O 1 D 2 D 3 D D D D D D D O D D D D D D D D
----------------------------------------------------------------------------------------------------------_
/ 208 206 204 202 200 198 196 194 192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 |_
/ 207 205 203 201 199 197 195 193 191 189 187 185 183 181 179 177 175 173 171 169 167 165 163 161 159 157 |
#TCK | 1 156 | ^DATA0
^CONF_DONE | 2 155 | ^DCLK
^nCEO | 3 154 | ^nCE
#TDO | 4 153 | #TDI
VCCIO | 5 152 | VCCINT
GND | 6 151 | GND
RESERVED | 7 150 | RESERVED
RESERVED | 8 149 | RESERVED
clk_1khz | 9 148 | RESERVED
RESERVED | 10 147 | RESERVED
RESERVED | 11 146 | VCCIO
RESERVED | 12 145 | GND
RESERVED | 13 144 | RESERVED
RESERVED | 14 143 | RESERVED
RESERVED | 15 142 | RESERVED
RESERVED | 16 141 | RESERVED
RESERVED | 17 140 | RESERVED
RESERVED | 18 139 | RESERVED
RESERVED | 19 138 | VCCIO
GND | 20 137 | GND
VCCINT | 21 136 | RESERVED
VCCIO | 22 135 | RESERVED
GND | 23 134 | RESERVED
RESERVED | 24 133 | RESERVED
RESERVED | 25 132 | RESERVED
RESERVED | 26 131 | RESERVED
RESERVED | 27 EP1K30QC208-3 130 | VCCINT
RESERVED | 28 129 | GND
RESERVED | 29 128 | RESERVED
RESERVED | 30 127 | RESERVED
RESERVED | 31 126 | RESERVED
GND | 32 125 | RESERVED
VCCINT | 33 124 | VCCINT
VCCIO | 34 123 | GND
GND | 35 122 | RESERVED
RESERVED | 36 121 | RESERVED
RESERVED | 37 120 | RESERVED
alarm | 38 119 | RESERVED
RESERVED | 39 118 | VCCIO
RESERVED | 40 117 | GND
RESERVED | 41 116 | RESERVED
VCCIO | 42 115 | RESERVED
GND | 43 114 | RESERVED
RESERVED | 44 113 | RESERVED
RESERVED | 45 112 | RESERVED
RESERVED | 46 111 | RESERVED
RESERVED | 47 110 | VCCIO
VCCINT | 48 109 | GND
GND | 49 108 | ^MSEL0
#TMS | 50 107 | ^MSEL1
#TRST | 51 106 | VCCINT
^nSTATUS | 52 105 | ^nCONFIG
| 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 _|
\ 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 |
\-----------------------------------------------------------------------------------------------------------
R R R R R R G R R R R R R V R R R R R V R R s G V G G G G G R V r R k R e m V b a R R R R V R R R R R R
E E E E E E N E E E E E E C E E E E E C E E e N C N N N N N E C e E e E n o C e l E E E E C E E E E E E
S S S S S S D S S S S S S C S S S S S C S S l D C D D D D D S C s S y S t d C g a S S S S C S S S S S S
E E E E E E E E E E E E I E E E E E I E E I E I e E u E e e I e r E E E E I E E E E E E
R R R R R R R R R R R R O R R R R R N R R N R O t R p R r N n m R R R R O R R R R R R
V V V V V V V V V V V V V V V V V T V V T V V V T d _ V V V V V V V V V V
E E E E E E E E E E E E E E E E E E E E E E s E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D D D w D D D D D D D D D D
i
t
c
h
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: c:\max2work\clock1\alarm_clock.rpt
alarm_clock
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A19 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 1/2 0/2 4/22( 18%)
A23 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 10/22( 45%)
A28 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
A31 8/ 8(100%) 6/ 8( 75%) 7/ 8( 87%) 0/2 0/2 5/22( 22%)
B1 7/ 8( 87%) 0/ 8( 0%) 5/ 8( 62%) 2/2 1/2 9/22( 40%)
B2 7/ 8( 87%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 19/22( 86%)
B3 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 2/2 1/2 9/22( 40%)
B4 7/ 8( 87%) 0/ 8( 0%) 7/ 8( 87%) 0/2 0/2 5/22( 22%)
B5 7/ 8( 87%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 16/22( 72%)
B6 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 4/22( 18%)
B7 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 1/2 10/22( 45%)
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