📄 ring.rpt
字号:
Total: 0 0 0 0 0 0 0 6 5 2 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20/0
Device-Specific Information: d:\progra~1\maxplus2\maxplusworks\clock1\ring.rpt
ring
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
148 - - A -- INPUT ^ 0 0 0 1 alarm_hourhdis0
144 - - A -- INPUT ^ 0 0 0 1 alarm_hourhdis1
46 - - C -- INPUT ^ 0 0 0 1 alarm_hourldis0
85 - - - 11 INPUT ^ 0 0 0 1 alarm_hourldis1
86 - - - 11 INPUT ^ 0 0 0 1 alarm_hourldis2
18 - - A -- INPUT ^ 0 0 0 1 alarm_hourldis3
94 - - - 07 INPUT ^ 0 0 0 1 alarm_minhdis0
164 - - - 04 INPUT ^ 0 0 0 1 alarm_minhdis1
167 - - - 06 INPUT ^ 0 0 0 1 alarm_minhdis2
119 - - C -- INPUT ^ 0 0 0 1 alarm_minldis0
112 - - C -- INPUT ^ 0 0 0 1 alarm_minldis1
100 - - - 03 INPUT ^ 0 0 0 1 alarm_minldis2
159 - - - 02 INPUT ^ 0 0 0 1 alarm_minldis3
174 - - - 09 INPUT ^ 0 0 0 1 alarm_switch
41 - - C -- INPUT ^ 0 0 0 1 freq_h
38 - - C -- INPUT ^ 0 0 0 1 freq_l
12 - - A -- INPUT ^ 0 0 0 1 hourhdis0
11 - - A -- INPUT ^ 0 0 0 1 hourhdis1
44 - - C -- INPUT ^ 0 0 0 1 hourldis0
97 - - - 05 INPUT ^ 0 0 0 1 hourldis1
120 - - C -- INPUT ^ 0 0 0 1 hourldis2
19 - - A -- INPUT ^ 0 0 0 1 hourldis3
184 - - - -- INPUT ^ 0 0 0 3 minhdis0
78 - - - -- INPUT ^ 0 0 0 2 minhdis1
182 - - - -- INPUT ^ 0 0 0 3 minhdis2
183 - - - -- INPUT ^ 0 0 0 3 minldis0
179 - - - 12 INPUT ^ 0 0 0 2 minldis1
102 - - - 02 INPUT ^ 0 0 0 2 minldis2
79 - - - -- INPUT ^ 0 0 0 3 minldis3
101 - - - 03 INPUT ^ 0 0 0 1 RESET
116 - - C -- INPUT ^ 0 0 0 2 sechdis0
89 - - - 09 INPUT ^ 0 0 0 2 sechdis1
80 - - - -- INPUT ^ 0 0 0 2 sechdis2
96 - - - 05 INPUT ^ 0 0 0 1 secldis0
47 - - C -- INPUT ^ 0 0 0 2 secldis1
39 - - C -- INPUT ^ 0 0 0 2 secldis2
92 - - - 08 INPUT ^ 0 0 0 2 secldis3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\progra~1\maxplus2\maxplusworks\clock1\ring.rpt
ring
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
122 - - C -- OUTPUT 0 1 0 0 ALARM
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\progra~1\maxplus2\maxplusworks\clock1\ring.rpt
ring
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - C 09 OR2 s ! 3 0 0 1 ~391~1
- 8 - C 09 AND2 s 2 2 0 1 ~391~2
- 4 - C 11 AND2 s 3 1 0 1 ~391~3
- 5 - C 11 AND2 2 1 0 2 :391
- 1 - C 09 AND2 s 4 0 0 2 ~426~1
- 6 - C 09 AND2 s 3 1 0 1 ~426~2
- 2 - C 11 AND2 s 3 1 0 1 ~426~3
- 3 - C 11 AND2 s 3 1 0 1 ~426~4
- 4 - C 09 OR2 s 4 0 0 1 ~474~1
- 1 - C 08 OR2 s 4 0 0 1 ~474~2
- 3 - C 08 OR2 s 4 0 0 1 ~474~3
- 4 - C 08 OR2 s 4 0 0 1 ~474~4
- 5 - C 08 AND2 s 0 4 0 1 ~474~5
- 1 - A 10 OR2 s 4 0 0 1 ~474~6
- 2 - A 10 OR2 s 2 1 0 1 ~474~7
- 6 - C 08 OR2 s 4 0 0 1 ~474~8
- 2 - C 08 AND2 1 3 0 1 :474
- 6 - C 11 AND2 s 1 1 0 1 ~505~1
- 7 - C 11 OR2 1 3 0 1 :505
- 1 - C 11 OR2 2 2 1 0 :511
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\progra~1\maxplus2\maxplusworks\clock1\ring.rpt
ring
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 6/ 96( 6%) 0/ 48( 0%) 0/ 48( 0%) 6/16( 37%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 18/ 96( 18%) 13/ 48( 27%) 0/ 48( 0%) 10/16( 62%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
09: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\progra~1\maxplus2\maxplusworks\clock1\ring.rpt
ring
** EQUATIONS **
alarm_hourhdis0 : INPUT;
alarm_hourhdis1 : INPUT;
alarm_hourldis0 : INPUT;
alarm_hourldis1 : INPUT;
alarm_hourldis2 : INPUT;
alarm_hourldis3 : INPUT;
alarm_minhdis0 : INPUT;
alarm_minhdis1 : INPUT;
alarm_minhdis2 : INPUT;
alarm_minldis0 : INPUT;
alarm_minldis1 : INPUT;
alarm_minldis2 : INPUT;
alarm_minldis3 : INPUT;
alarm_switch : INPUT;
freq_h : INPUT;
freq_l : INPUT;
hourhdis0 : INPUT;
hourhdis1 : INPUT;
hourldis0 : INPUT;
hourldis1 : INPUT;
hourldis2 : INPUT;
hourldis3 : INPUT;
minhdis0 : INPUT;
minhdis1 : INPUT;
minhdis2 : INPUT;
minldis0 : INPUT;
minldis1 : INPUT;
minldis2 : INPUT;
minldis3 : INPUT;
RESET : INPUT;
sechdis0 : INPUT;
sechdis1 : INPUT;
sechdis2 : INPUT;
secldis0 : INPUT;
secldis1 : INPUT;
secldis2 : INPUT;
secldis3 : INPUT;
-- Node name is 'ALARM'
-- Equation name is 'ALARM', type is output
ALARM = _LC1_C11;
-- Node name is '~391~1'
-- Equation name is '~391~1', location is LC2_C9, type is buried.
-- synthesized logic cell
!_LC2_C9 = _LC2_C9~NOT;
_LC2_C9~NOT = LCELL( _EQ001);
_EQ001 = !secldis3
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -