📄 freq_dou.rpt
字号:
- 5 - B 02 DFFE + 0 0 0 8 cnt0 (:12)
- 4 - B 07 OR2 s 0 4 0 1 ~39~1
- 2 - B 07 OR2 s 0 4 0 5 ~39~2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: c:\max2work\clock0\freq_dou.rpt
freq_dou
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 6/ 96( 6%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\max2work\clock0\freq_dou.rpt
freq_dou
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 10 clk
Device-Specific Information: c:\max2work\clock0\freq_dou.rpt
freq_dou
** EQUATIONS **
clk : INPUT;
-- Node name is ':12' = 'cnt0'
-- Equation name is 'cnt0', location is LC5_B2, type is buried.
cnt0 = DFFE(!cnt0, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':11' = 'cnt1'
-- Equation name is 'cnt1', location is LC1_B2, type is buried.
cnt1 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = cnt0 & !cnt1
# !cnt0 & cnt1 & _LC2_B7;
-- Node name is ':10' = 'cnt2'
-- Equation name is 'cnt2', location is LC4_B2, type is buried.
cnt2 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !cnt0 & cnt2
# !cnt1 & cnt2
# cnt0 & cnt1 & !cnt2;
-- Node name is ':9' = 'cnt3'
-- Equation name is 'cnt3', location is LC8_B7, type is buried.
cnt3 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !cnt2 & cnt3
# !cnt0 & cnt3
# !cnt1 & cnt3
# cnt0 & cnt1 & cnt2 & !cnt3;
-- Node name is ':8' = 'cnt4'
-- Equation name is 'cnt4', location is LC5_B7, type is buried.
cnt4 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = cnt0 & cnt4 & !_LC3_B7
# cnt4 & _LC2_B7 & !_LC3_B7
# !cnt4 & _LC3_B7
# !cnt0 & !_LC2_B7 & _LC3_B7;
-- Node name is ':7' = 'cnt5'
-- Equation name is 'cnt5', location is LC6_B2, type is buried.
cnt5 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = cnt0 & cnt5 & !_LC1_B7
# cnt5 & !_LC1_B7 & _LC2_B7
# !cnt5 & _LC1_B7
# !cnt0 & _LC1_B7 & !_LC2_B7;
-- Node name is ':6' = 'cnt6'
-- Equation name is 'cnt6', location is LC7_B7, type is buried.
cnt6 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = !cnt5 & cnt6
# cnt6 & !_LC1_B7
# cnt5 & !cnt6 & _LC1_B7;
-- Node name is ':5' = 'cnt7'
-- Equation name is 'cnt7', location is LC6_B7, type is buried.
cnt7 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = !cnt5 & cnt7
# cnt7 & !_LC1_B7
# !cnt6 & cnt7
# cnt5 & cnt6 & !cnt7 & _LC1_B7;
-- Node name is ':4' = 'cnt_10hz'
-- Equation name is 'cnt_10hz', location is LC2_B2, type is buried.
cnt_10hz = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = cnt0 & cnt_10hz
# cnt_10hz & _LC2_B7
# !cnt0 & !cnt_10hz & !_LC2_B7;
-- Node name is 'dou_clk'
-- Equation name is 'dou_clk', type is output
dou_clk = _LC8_B2;
-- Node name is '|LPM_ADD_SUB:124|addcore:adder|:83' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B7', type is buried
_LC3_B7 = LCELL( _EQ009);
_EQ009 = cnt0 & cnt1 & cnt2 & cnt3;
-- Node name is '|LPM_ADD_SUB:124|addcore:adder|:87' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B7', type is buried
_LC1_B7 = LCELL( _EQ010);
_EQ010 = cnt4 & _LC3_B7;
-- Node name is ':2'
-- Equation name is '_LC8_B2', type is buried
_LC8_B2 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = !cnt0 & cnt_10hz & !_LC2_B7
# cnt0 & _LC8_B2
# _LC2_B7 & _LC8_B2;
-- Node name is '~39~1'
-- Equation name is '~39~1', location is LC4_B7, type is buried.
-- synthesized logic cell
_LC4_B7 = LCELL( _EQ012);
_EQ012 = !cnt4
# !cnt5
# cnt7
# cnt6;
-- Node name is '~39~2'
-- Equation name is '~39~2', location is LC2_B7, type is buried.
-- synthesized logic cell
_LC2_B7 = LCELL( _EQ013);
_EQ013 = _LC4_B7
# !cnt1
# cnt2
# cnt3;
Project Information c:\max2work\clock0\freq_dou.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 17,513K
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