📄 debouncing.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library altera;
use altera.maxplus2.all;
entity debouncing is
port(
d_in:in std_logic;
d_out:out std_logic;
clk:in std_logic);
end debouncing;
architecture behavior of debouncing is
signal vcc,inv_d:std_logic;
signal d1,d0:std_logic;
signal q1,q0:std_logic;
begin
vcc<='1';
inv_d<=not d_in;
dff1:dff port map(d=>vcc,Q=>q0,clk=>clk,clrn=>inv_d,prn=>vcc);
dff2:dff port map(d=>vcc,Q=>q1,clk=>clk,clrn=>q0,prn=>vcc);
process(clk)
begin
if clk'event and clk='1' then
d0<=not q1;
d1<=d0;
end if;
end process;
d_out<=not(d1 and not d0);
end behavior;
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