zerorunlengthcoder.v

来自「encoder jpeg project」· Verilog 代码 · 共 93 行

module ZeroRunLengthCoder  (  DataIn, 
                              Clock, 
                              Reset, 
                              Start, 
                              Enable, 
                              EndData, 
                              DC, 
                              AC, 
                              ZRL, 
                              EOB, 
                              EOB2, 
                              ZCout, 
				  CoeffOut
                           );

//                MODULE INPUTS
input [10:0]       DataIn;                 // data input to the entropy encoder
input              Clock;                  // clock signal
input              Reset;                  // system wide low asserted reset signal
input              Start;                  // signals start of valid data
input              EndData;                // signals the end of valid data
input              Enable;                 // system wide enable signal

//                MODULE OUTPUTS
output             DC;                     // signals a DC coefficient at output 
output             AC;                     // signals an AC coefficient at output 
output             EOB;                    // signals an EOB condition (see txt file) 
output             EOB2;                   // signals the 64th value at output 
output             ZRL;                    // signals a count of 16 zeros
output [3:0]       ZCout;                  // the zero runlength output
output [11:0]      CoeffOut;               // the coefficient output

//instantiation of controller 
RLCCtrl controller  (   Clock, 
			   Reset, 
			   Start,
                        Enable, 
                        EndData, 
                        Countgey, 
                        Run16, 
                        ZeroCoeff, 
                        LoadData, 
                        RSTCount, 
                        IncrCount, 
                        MuxSel, 
                		LoadMuxOut, 
                        LoadPDC, 
                        LoadZC, 
                        IncrZC, 
                        RSTZC,  
                        RSTPDC, 
                        sDC, 
                        sAC, 
                        sZRL, 
                        sEOB, 
                        sEOB2, 
                        LoadCoeffOut, 
                        RSTZCO);

//instantiation of architecture
RLCArch architecture(   Clock,
                    Reset, 
                    DataIn,  
                    LoadData, 
                    RSTCount, 
                    IncrCount, 
                    MuxSel, 
                    LoadMuxOut, 
                    LoadPDC, 
                    LoadZC, 
                    IncrZC, 
                    RSTZC, 
                    RSTPDC, 
                    sDC, 
                    sAC, 
                    sZRL, 
                    sEOB, 
                    sEOB2, 
                    LoadCoeffOut, 
                    RSTZCO, 
                    Countgey, 
                    Run16, 
                    ZeroCoeff, 
                    DC, 
                    AC, 
                    ZRL, 
                    EOB, 
                    EOB2, 
                    CoeffOut, 
                    Zcout
                  );
endmodule