huffmanencoder.v

encoder jpeg project

/*******************************************************************/
/*	This module implements the Huffman encoder stage of the     */
/*	Entropy encoder 			 	  		     */
/*******************************************************************/


module  HuffmanEncoder  (   Clock, 
                            Reset, 
                            Enable, 
                            ValidSignal, 
                            CoefficientIn, 
                            CategoryIn, 
                            RunLengthIn, 
                            DCin, 
                            ACin, 
                            EOBin, 
                            EOB2in, 
                            ZRLin, 
                            Huffman, 
                            CategoryOut, 
                            RunLengthOut, 
                            CoefficientOut, 
                            EOB2out, 
                            ValidOutput, 
                        );

//                 MODULE INPUTS
input 		Clock; 
input		Reset;
input		Enable; 
input 		ValidSignal;	// Signal indicating new data
input [10:0] 	CoefficientIn; // Coefficient input from strip logic	
input [3:0] 	CategoryIn;   // Category input from strip logic
input [3:0]   RunLengthIn;  // Runlength input from strip logic
input         Dcin;         // Status bits input
input         Acin; 
input 	       EOBin; 
input 		ZRLin;
input 		EOB2in;

//                MODULE OUTPUTS
output [3:0] 	CategoryOut; 
output [3:0]  RunLengthOut;
output [10:0] CoefficientOut; 
output [19:0] Huffman;		// Huffman code and code length
output 	EOB2out;		// BlkEnd signal 
output 	ValidOutput; 	// Signal indicating valid code 
						// output
reg 		ValidOutput;
reg [19:0] 	Huffman;

//                    INTERNAL REGISTERS

// Register for state machine outputs
reg  		ResetAll; 		       // Signals reset of all internal
						// registers 
reg		LoadInput; 		      // Signals loading of new data
reg		LoadACOut;		      // Signals loading of AC ROM out
reg		LoadDCOut; 		      // Signals loading of DC ROM out
reg		OutputValid;               // Sets the ValidOutput flag    

// Registers for architecture implementation
reg [10:0] 		Coefficient1; 	// Registers making up the  
reg [10:0]		Coefficient2;	       // internal stages of the 
reg [3:0] 		RunLength1; 	       // Huffman coder stage
reg [3:0] 		RunLength2;
reg [3:0] 		Category1; 
reg [3:0]		Category2;
reg 			EOB21; 
reg			EOB22;
reg 			DC; 
reg			AEZ;
wire 			aez;			// Signals presense of either
						// AC, EOB or ZRL status signal
reg 			CurrState; 		// Current state register of FSM
reg			NextState;		
wire [19:0] 	       ACCodeOut; 		// Output of AC codes LUT
wire [19:0]		DCCodeOut;		// Output of DC codes LUT

parameter 		RESET = 1'b0, 
                     ST1=1'b1;

//	Instantiations of LUTs 
AROMDC DCLut(Category1, DCCodeOut);
AROMAC ACLut({RunLength1,Category1}, ACCodeOut);
 
// Assignments of output wires
assign CoefficientOut = Coefficient2;
assign RunLengthOut = RunLength2;
assign CategoryOut = Category2;
assign EOB2out = EOB22;

assign aez = ACin | EOBin | ZRLin;

// Current state logic of FSM
always@(posedge Clock or posedge Reset)
  begin: FSM_SEQ
  if(!Reset)
    CurrState = RESET;
  else
    CurrState = NextState;
  end

// Next state and output logic of FSM
always@(CurrState or ValidSignal or Enable)
  begin: FSM_COMB
  ResetAll = 0;
  LoadInput = 0;
  LoadACOut = 0;
  LoadDCOut = 0;
  OutputValid = 0;          
  
  case(CurrState)

    RESET:  begin
            ResetAll = 1;            
            NextState = ST1;
            end

    ST1:    begin
            if(ValidSignal & Enable)
              begin
              LoadInput = 1;
              if(AEZ)
                begin
                LoadACOut = 1;
                OutputValid = 1;
                end
              else if(DC)
                begin
                LoadDCOut = 1;
                OutputValid = 1;
                end
              else
                begin
                OutputValid = 0;
                end
              NextState = ST1;
              end
            else
              NextState = ST1;
            end

    default: NextState = RESET;

  endcase
  end

// clocked always blocks implementing the register assignments
always@(posedge Clock)
  begin
    if(ResetAll)
      begin
      Coefficient1 <= 0;
      RunLength1 <= 0;
      Category1 <= 0;
      Coefficient2 <= 0;
      RunLength2 <= 0;
      Category2 <= 0;
      EOB21 <= 0;
      EOB22 <= 0;
      DC <= 0;
      AEZ <= 0;
      end 
    else if(LoadInput)
      begin
      Coefficient1 <= CoefficientIn;
      RunLength1 <= RunLengthIn;
      Category1 <= CategoryIn;
      DC <= DCin;
      AEZ <= aez;
      Coefficient2 <= Coefficient1;
      RunLength2 <= RunLength1;
      Category2 <= Category1;
      EOB21 <= EOB2in;
      EOB22 <= EOB21;
      end
    else if(EOB22)
     	EOB22 <= 0;
  end 
 
always@(posedge Clock)
  begin
  if(LoadACOut)
    Huffman <= ACCodeOut;
  else if(LoadDCOut)
    Huffman <= DCCodeOut;
  else 
    Huffman <= 0;
  end

always@(posedge Clock)
  if(OutputValid)
    ValidOutput <= 1;
  else
    ValidOutput <= 0;
endmodule