rlcctrl.v

encoder jpeg project

/*******************************************************************/
/*	This module implements the controller for the Run Length 	 */
/*	Encoder stage of the Entropy encoder 				 */
/*******************************************************************/

module RLCCtrl  (	      Clock, 
				Reset, 
				Start,
                        Enable, 
                        EndData, 
                        Countgey, 
                        Run16, 
                        ZeroCoeff, 
                        LoadData, 
                        RSTCount, 
                        IncrCount, 
                        MuxSel, 
                		LoadMuxOut, 
                        LoadPDC, 
                        LoadZC, 
                        IncrZC, 
                        RSTZC,  
                        RSTPDC, 
                        sDC, 
                        sAC, 
                        sZRL, 
                        sEOB, 
                        sEOB2, 
                        LoadCoeffOut, 
                        RSTZCO);

//                   MODULE INPUTS                      

input 		Clock;		// Clock signal
input 		Reset; 		// Low asserted system-wide reset 
input 		Start;		// Signal implying start of data
input 		Enable; 		// System-wide enable signal
input 		EndData; 		// Signal implying end of data
input 		Countgey; 		// Signal implying Count has 
						// its max value
input 		Run16; 		// Sinal implying zero count has
						// reached its max value
input 		ZeroCoeff;		// Signal implying a zero 
						// coefficient
//                   MODULE OUTPUTS

output 	LoadData;		// Signals loading of new data
output 	RSTCount; 		// Resets the counter value
output 	IncrCount; 		// Increments the counter value
output 	MuxSel;		// Mux selector input
output 	LoadMuxOut; 	// Signals loading of mux output
output 	LoadPDC; 		// Signals loading of DCI-1 value
output 	LoadZC; 		// Signals loading of zero count
output 	IncrZC; 		// Increments the zero count
output 	RSTZC; 		// Resets the zero count
output 	RSTPDC; 		// Resets the DCI-1 
output 	sDC; 			// Sets the DC status signal
output 	sAC; 			// Sets the AC status signal
output 	sZRL; 		// Sets the ZRL status signal
output 	sEOB; 		// Sets the EOB status signal
output 	sEOB2; 		// Sets the BlkEnd status signal
output 	LoadCoeffOut; 	// Signals loading of Data out
output 	RSTZCO; 		// Resets the zero counter out

reg 		LoadData; 
reg 		RSTCount; 
reg 		IncrCount; 
reg 		MuxSel;
reg 		LoadMuxOut; 
reg 		LoadPDC; 
reg 		LoadZC; 
reg 		IncrZC; 
reg 		RSTZC; 
reg 		RSTPDC; 
reg 		sDC; 
reg 		sAC; 
reg 		sZRL; 
reg 		sEOB; 
reg 		sEOB2; 
reg 		LoadCoeffOut; 
reg 		RSTZCO;

reg [1:0] 	CurrState;			// FSM Current state register  
reg [1:0]	NextState;			// FSM Next state register

parameter [1:0] 	ST0 = 2'b00,	// FSM State names
                  ST1 = 2'b01, 
                  ST2 = 2'b10, 
                  ST3 = 2'b11;

parameter 		DC = 1'b0, 		// Mux inputs
                  AC = 1'b1;

// FSM current state logic
always@(posedge Clock or negedge Reset)
 	begin: FSM_SEQ
 	if(!Reset)
   		CurrState = ST0;
 	else
    		CurrState = NextState;
  	end

// FSM next state and output logic
always @ (	CurrState or  Start or Enable or EndData or Countgey or Run16 or ZeroCoeff 	)
 	begin: FSM_COMB
  	LoadData=0; 
  	RSTCount=0; 
  	IncrCount=0; 
  	MuxSel=0;
  	LoadMuxOut=0; 
  	LoadPDC=0;
  	LoadZC=0;   
  	IncrZC=0; 
  	RSTZC=0; 
  	RSTPDC=0;
  	sDC=0; 
  	sAC=0; 
  	sZRL=0; 
  	sEOB=0; 
  	LoadCoeffOut=0;
  	RSTZCO = 0;
  	sEOB2 = 0;
  
  	case(CurrState)

      ST0:  if(Start & Enable)	// if arrival of data has begun
            	begin
            	LoadData = 1;
            	NextState = ST1;
            	end
      	else
            	begin			// else remain in reset state
            	RSTCount = 1;
            	RSTZC = 1;
            	RSTPDC = 1;
            	NextState = ST0;
            	end

    	ST1:	if(Enable)			// generate signals for latching
    			begin			// current DC coefficient and 
          		LoadData = 1;	// select the difference of DC
          		LoadPDC = 1;	// coefficients as the mux output
          		MuxSel = DC;
          		LoadMuxOut = 1;
          		NextState = ST2;
          		end
          	else
          		NextState = ST1;

    	ST2:  if(Enable)			// set the DC status signal and
		    	Begin			// begin the count of incoming
          		LoadData = 1;	// coefficients 
          		MuxSel = AC;	
          		LoadMuxOut = 1;
          		LoadCoeffOut = 1;
			RSTZCO = 1;
          		sDC = 1;
          		IncrCount = 1;
          		NextState = ST3;
          		end
          	else
          		NextState = ST2;

    	ST3:  if(Enable)			
		    	begin
          		LoadData = 1;
          		MuxSel = AC;
          		LoadMuxOut = 1;
          		LoadCoeffOut = 1;
          		IncrCount = 1;
          		if(ZeroCoeff)		// if coefficient is zero
            		begin
            		  if(Countgey)	// Count equals 64?	
              			Begin		
              			sEOB = 1;	// output EOB status
              			sEOB2 = 1;	// output BlkEnd status
              			if(EndData)	// if this is last data
                				NextState = ST0; //finish work
              			else
                				begin
                 				LoadPDC = 1;	// prepare	
                 				MuxSel = DC;	// for new
		     				RSTZC = 1;		// block
	           		 		RSTZCO = 1;	
                 				NextState = ST2;
                 				end //end else 
              			end  //end if(Countgey)
            		  else
              			begin		// if block not ended
              			IncrZC = 1; // adjust the zero count
					LoadZC = 1;	// load ZC value
              			if(Run16)
                				sZRL = 1;
              			NextState = ST3;
              			end //end else
            		end // end if(ZeroCoeff)
          		else	 
            		begin			// if coefficient non-zero
            		RSTZC = 1;		// reset ZC
            		LoadZC = 1;       // load current value    
            		sAC = 1;		// set AC status
            		if(Countgey)	// Count equals 64?	
              			begin 
              			sEOB2 = 1;	// set BlkEnd status
              			if(EndData)	// if this is last data
              				NextState = ST0;	// finish work
              			else
              				begin		     			
		     				LoadPDC = 1;	// else 
                				MuxSel = DC;	// prepare for
						NextState = ST2; 	// new block
                				end //end else                 
		  			end //end if(Countgey)
            		else
              			NextState = ST3;
            		end //end else
          		end //end if(Enable)
          	else
          		NextState = ST3;
          	
    	default: NextState = ST0;
    	endcase
end

endmodule