rlcarch.v

encoder jpeg project

/*******************************************************************/
/*	This module implements the architecture for the Run Length 	 */
/*	Encoder stage of the Entropy encoder 				 */
/*******************************************************************/
module  RLCArch (   Clock,
                    Reset, 
                    DataIn,  
                    LoadData, 
                    RSTCount, 
                    IncrCount, 
                    MuxSel, 
                    LoadMuxOut, 
                    LoadPDC, 
                    LoadZC, 
                    IncrZC, 
                    RSTZC, 
                    RSTPDC, 
                    sDC, 
                    sAC, 
                    sZRL, 
                    sEOB, 
                    sEOB2, 
                    LoadCoeffOut, 
                    RSTZCO, 
                    Countgey, 
                    Run16, 
                    ZeroCoeff, 
                    DC, 
                    AC, 
                    ZRL, 
                    EOB, 
                    EOB2, 
                    CoeffOut, 
                    Zcout
                  );

//                  MODULE INPUTS
input         Clock;		       // Clock signal 
input 	       Reset; 		// Low asserted system-wide reset
input 		LoadData; 		// Signals loading of new data
input 		RSTCount; 		// Resets the coefficient counter
input 		IncrCount; 		// Increments coefficient counter 
input 		MuxSel;		// Mux Select
input 		LoadMuxOut; 	       // Signals loading of mux output
input 		LoadPDC; 		// Signals loading of DC value
input 		LoadZC;		// Signals loading of zero count 
input 		IncrZC; 		// Increments the zero count
input 		RSTZC; 		// Resets the zero count
input 		RSTPDC; 		// Resets the DCI-1
input 		sDC; 			// Set the DC status flag
input 		sAC; 			// Set the AC status flag
input 		sZRL; 		       // Set the ZRL status flag
input 		sEOB; 		       // Set the EOB status flag
input 		sEOB2; 		// Set the BlkEnd status flag
input 		LoadCoeffOut; 	// Signals loading of data out
input 		RSTZCO; 		// Resets the ZC output register
input [11:0] 	DataIn;		// Data input from Zig Zag stage

//                 MODULE OUTPUTS
output 	Countgey; 		// Indicates counter==63
output 	Run16; 		// Indicates zero count==16	
output 	ZeroCoeff; 		// Indicates a zero coefficient
output 	DC; 			// DC status output
output 	AC; 			// AC status output
output 	ZRL;			// ZRL status output
output 	EOB; 			// EOB status output
output		EOB2; 		       // BlkEnd status output
output [11:0] CoeffOut;		// Processed coefficient output 
output [3:0] 	ZCout;		       // zero count output

reg  			DC;			
reg	 		AC; 
reg 			ZRL; 
reg 			EOB; 
reg 			EOB2; 
reg [11:0] 		CoeffOut;
reg [3:0]		ZCout;

//              INTERNAL VARIABLES
reg [11:0] 		Data;		// Register for input data 
reg [11:0]		MuxOutReg; 	// Holds the output of mux
reg [11:0]		PDC;		// Holds the DCI-1 value
reg [5:0] 		Count;		// Counter for coefficients
reg [3:0] 		ZC; 		 // zero counter
wire [11:0] 	       MuxOut; 	// 2:1 mux output	
wire [11:0]		SubPDC;      // Subtractor output
wire [11:0]		SubMSB;      // output stage subtractor

//Combinational logic implementation such as Muxes, Adders/Subtractors and Comparators
assign MuxOut = MuxSel ? Data:SubPDC;	// 2:1 mux
assign SubPDC = Data - PDC;			// subtractor for DCI - DCI-1 
assign SubMSB = MuxOutReg - MuxOutReg[11];// For decrementing 杤e 
						// valued coefficients

// Comparator implementations
assign Countgey = Count<63?0:1;		// Comparator for count
assign ZeroCoeff = MuxOutReg==0?1:0;	// zero Comparator 	
assign Run16 = ZC==15?1:0;			// runlength comparator  

//clocked always blocks implementing the register assignments
always@(posedge Clock)
begin
  	if(LoadData)
    		Data <= DataIn;
  	end

always@(posedge Clock)
begin
  	if(LoadMuxOut)
    		MuxOutReg <= MuxOut;
  	end

always@(posedge Clock)
begin
  	if(LoadCoeffOut)
    		CoeffOut <= SubMSB;
  	end

always@(posedge Clock)
begin
  	if(RSTPDC)
    		PDC <= 0;    
  	if(LoadPDC)
    		PDC <= Data;
  	end

always@(posedge Clock)
begin
  	if(IncrCount)
    		Count <= Count + 1;	
  	if(RSTCount)
		begin
    		Count <= 0;
		Over <= 0;
		end
  	end

always@(posedge Clock)
  	begin
  	if(IncrZC)
    		ZC <= ZC + 1;
  	if(LoadZC)
    		ZCout <= ZC;
  	if(RSTZC)
    		ZC <= 0;	
  	if(RSTZCO)
    		ZCout <= 0;
  	end

always@(posedge Clock)
begin
  	if(sAC)
    		AC <= 1;
  	else
    		AC <= 0;

  	if(sDC)
    		DC <= 1;
  	else
    		DC <= 0;

  	if(sZRL)
    		ZRL <= 1;
  	else
    		ZRL <= 0;

  	if(sEOB)
    		EOB <= 1;
  	else
    		EOB <= 0;

	if(sEOB2)
		EOB2 <= 1;
	else
		EOB2 <= 0;
end	
endmodule