📄 mt54w512h36.vhd
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---------------------------------------------------------------------------------- File Name: mt54w512h36.vhd---------------------------------------------------------------------------------- Copyright (C) 2002, 2003 Free Model Foundry; http://www.FreeModelFoundry.com-- -- This program is free software; you can redistribute it and/or modify-- it under the terms of the GNU General Public License version 2 as-- published by the Free Software Foundation.-- -- MODIFICATION HISTORY:-- -- version: | author: | mod date: | changes made:-- V1.0 R. Munden 02 Sep 12 Initial releas -- V1.1 M.Marinkovic 02 Nov 25 Added memory file read, DLL-- V1.2 R. Munden 03 May 25 Fixed output timing in K mode-- V1.3 R. Munden 03 Jun 26 Rewrote DLL phase lock in C mode-- V1.4 R. Munden 03 Jul 30 Rewrote DLL phase lock in K mode-- V1.5 R. Munden 03 Oct 10 Enhanced memory preload capability-- V1.6 R. Munden 03 Nov 05 Fixed memory preload capability-- enhanced DLLs-- V1.7 R. Munden 04 MAR 26 Fixed DLLs to work with stopped clocks-- V1.8 R. Munden 06 Feb 11 Improved memory preload method---------------------------------------------------------------------------------- PART DESCRIPTION:-- -- Library: RAM-- Technology: CMOS-- Part: MT54W512H36-- -- Description: QDR II SRAM 512K x 36-- This model requires VITAL2000--------------------------------------------------------------------------------LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; USE STD.textio.ALL;LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.ALL;---------------------------------------------------------------------------------- ENTITY DECLARATION--------------------------------------------------------------------------------ENTITY mt54w512h36 IS GENERIC ( -- tipd delays: interconnect path delays tipd_DLLNeg : VitalDelayType01 := VitalZeroDelay01; tipd_ZQ : VitalDelayType01 := VitalZeroDelay01; tipd_A0 : VitalDelayType01 := VitalZeroDelay01; tipd_A1 : VitalDelayType01 := VitalZeroDelay01; tipd_A2 : VitalDelayType01 := VitalZeroDelay01; tipd_A3 : VitalDelayType01 := VitalZeroDelay01; tipd_A4 : VitalDelayType01 := VitalZeroDelay01; tipd_A5 : VitalDelayType01 := VitalZeroDelay01; tipd_A6 : VitalDelayType01 := VitalZeroDelay01; tipd_A7 : VitalDelayType01 := VitalZeroDelay01; tipd_A8 : VitalDelayType01 := VitalZeroDelay01; tipd_A9 : VitalDelayType01 := VitalZeroDelay01; tipd_A10 : VitalDelayType01 := VitalZeroDelay01; tipd_A11 : VitalDelayType01 := VitalZeroDelay01; tipd_A12 : VitalDelayType01 := VitalZeroDelay01; tipd_A13 : VitalDelayType01 := VitalZeroDelay01; tipd_A14 : VitalDelayType01 := VitalZeroDelay01; tipd_A15 : VitalDelayType01 := VitalZeroDelay01; tipd_A16 : VitalDelayType01 := VitalZeroDelay01; tipd_A17 : VitalDelayType01 := VitalZeroDelay01; tipd_D0 : VitalDelayType01 := VitalZeroDelay01; tipd_D1 : VitalDelayType01 := VitalZeroDelay01; tipd_D2 : VitalDelayType01 := VitalZeroDelay01; tipd_D3 : VitalDelayType01 := VitalZeroDelay01; tipd_D4 : VitalDelayType01 := VitalZeroDelay01; tipd_D5 : VitalDelayType01 := VitalZeroDelay01; tipd_D6 : VitalDelayType01 := VitalZeroDelay01; tipd_D7 : VitalDelayType01 := VitalZeroDelay01; tipd_D8 : VitalDelayType01 := VitalZeroDelay01; tipd_D9 : VitalDelayType01 := VitalZeroDelay01; tipd_D10 : VitalDelayType01 := VitalZeroDelay01; tipd_D11 : VitalDelayType01 := VitalZeroDelay01; tipd_D12 : VitalDelayType01 := VitalZeroDelay01; tipd_D13 : VitalDelayType01 := VitalZeroDelay01; tipd_D14 : VitalDelayType01 := VitalZeroDelay01; tipd_D15 : VitalDelayType01 := VitalZeroDelay01; tipd_D16 : VitalDelayType01 := VitalZeroDelay01; tipd_D17 : VitalDelayType01 := VitalZeroDelay01; tipd_D18 : VitalDelayType01 := VitalZeroDelay01; tipd_D19 : VitalDelayType01 := VitalZeroDelay01; tipd_D20 : VitalDelayType01 := VitalZeroDelay01; tipd_D21 : VitalDelayType01 := VitalZeroDelay01; tipd_D22 : VitalDelayType01 := VitalZeroDelay01; tipd_D23 : VitalDelayType01 := VitalZeroDelay01; tipd_D24 : VitalDelayType01 := VitalZeroDelay01; tipd_D25 : VitalDelayType01 := VitalZeroDelay01; tipd_D26 : VitalDelayType01 := VitalZeroDelay01; tipd_D27 : VitalDelayType01 := VitalZeroDelay01; tipd_D28 : VitalDelayType01 := VitalZeroDelay01; tipd_D29 : VitalDelayType01 := VitalZeroDelay01; tipd_D30 : VitalDelayType01 := VitalZeroDelay01; tipd_D31 : VitalDelayType01 := VitalZeroDelay01; tipd_D32 : VitalDelayType01 := VitalZeroDelay01; tipd_D33 : VitalDelayType01 := VitalZeroDelay01; tipd_D34 : VitalDelayType01 := VitalZeroDelay01; tipd_D35 : VitalDelayType01 := VitalZeroDelay01; tipd_RNeg : VitalDelayType01 := VitalZeroDelay01; tipd_WNeg : VitalDelayType01 := VitalZeroDelay01; tipd_BW0Neg : VitalDelayType01 := VitalZeroDelay01; tipd_BW1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_BW2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_BW3Neg : VitalDelayType01 := VitalZeroDelay01; tipd_K : VitalDelayType01 := VitalZeroDelay01; tipd_KNeg : VitalDelayType01 := VitalZeroDelay01; tipd_C : VitalDelayType01 := VitalZeroDelay01; tipd_CNeg : VitalDelayType01 := VitalZeroDelay01; tipd_TMS : VitalDelayType01 := VitalZeroDelay01; tipd_TDI : VitalDelayType01 := VitalZeroDelay01; tipd_TCK : VitalDelayType01 := VitalZeroDelay01; -- tpd delays -- tCLZ tpd_C_Q0 : VitalDelayType01Z := VitalZeroDelay01Z; -- tKC Var tpd_C_Q1 : VitalDelayType := 200 ps; -- tCCQ0 tpd_C_CQ : VitalDelayType01Z := VitalZeroDelay01Z; -- tpw values: pulse widths -- tKH tpw_K_posedge : VitalDelayType := UnitDelay; -- tKL tpw_K_negedge : VitalDelayType := UnitDelay; -- tperiod min (calculated as 1/max freq) -- tCYC tperiod_K : VitalDelayType := UnitDelay; -- tsetup values: setup times -- tSA tsetup_A0_K : VitalDelayType := UnitDelay; -- tSD tsetup_D0_K : VitalDelayType := UnitDelay; -- tSC, tSCDDR tsetup_RNeg_K : VitalDelayType := UnitDelay; -- thold values: hold times -- tHA thold_A0_K : VitalDelayType := UnitDelay; -- tHD thold_D0_K : VitalDelayType := UnitDelay; -- tHC, tHCDDR thold_RNeg_K : VitalDelayType := UnitDelay;--VITAL2000 -- tskew values: skew times -- tKHCH tskew_K_C : VitalDelayType := UnitDelay; -- tKHKH tskew_K_KNeg : VitalDelayType := UnitDelay; -- tKHKH tskew_KNeg_K : VitalDelayType := UnitDelay; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; SeverityMode : SEVERITY_LEVEL := WARNING; -- memory file to be loaded mem_file_name : STRING := "none"; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( DLLNeg : IN std_ulogic := 'U'; ZQ : IN std_ulogic := 'U'; A0 : IN std_ulogic := 'U'; A1 : IN std_ulogic := 'U'; A2 : IN std_ulogic := 'U'; A3 : IN std_ulogic := 'U'; A4 : IN std_ulogic := 'U'; A5 : IN std_ulogic := 'U'; A6 : IN std_ulogic := 'U'; A7 : IN std_ulogic := 'U'; A8 : IN std_ulogic := 'U'; A9 : IN std_ulogic := 'U'; A10 : IN std_ulogic := 'U'; A11 : IN std_ulogic := 'U'; A12 : IN std_ulogic := 'U'; A13 : IN std_ulogic := 'U'; A14 : IN std_ulogic := 'U'; A15 : IN std_ulogic := 'U'; A16 : IN std_ulogic := 'U'; A17 : IN std_ulogic := 'U'; D0 : IN std_ulogic := 'U'; D1 : IN std_ulogic := 'U'; D2 : IN std_ulogic := 'U'; D3 : IN std_ulogic := 'U'; D4 : IN std_ulogic := 'U'; D5 : IN std_ulogic := 'U'; D6 : IN std_ulogic := 'U'; D7 : IN std_ulogic := 'U'; D8 : IN std_ulogic := 'U'; D9 : IN std_ulogic := 'U'; D10 : IN std_ulogic := 'U'; D11 : IN std_ulogic := 'U'; D12 : IN std_ulogic := 'U'; D13 : IN std_ulogic := 'U'; D14 : IN std_ulogic := 'U'; D15 : IN std_ulogic := 'U'; D16 : IN std_ulogic := 'U'; D17 : IN std_ulogic := 'U'; D18 : IN std_ulogic := 'U'; D19 : IN std_ulogic := 'U'; D20 : IN std_ulogic := 'U'; D21 : IN std_ulogic := 'U'; D22 : IN std_ulogic := 'U'; D23 : IN std_ulogic := 'U'; D24 : IN std_ulogic := 'U'; D25 : IN std_ulogic := 'U'; D26 : IN std_ulogic := 'U'; D27 : IN std_ulogic := 'U'; D28 : IN std_ulogic := 'U'; D29 : IN std_ulogic := 'U'; D30 : IN std_ulogic := 'U'; D31 : IN std_ulogic := 'U'; D32 : IN std_ulogic := 'U'; D33 : IN std_ulogic := 'U'; D34 : IN std_ulogic := 'U'; D35 : IN std_ulogic := 'U'; RNeg : IN std_ulogic := 'U'; WNeg : IN std_ulogic := 'U'; BW0Neg : IN std_ulogic := 'U'; BW1Neg : IN std_ulogic := 'U'; BW2Neg : IN std_ulogic := 'U'; BW3Neg : IN std_ulogic := 'U'; K : IN std_ulogic := 'U'; KNeg : IN std_ulogic := 'U'; C : IN std_ulogic := 'U'; CNeg : IN std_ulogic := 'U'; TMS : IN std_ulogic := 'U'; TDI : IN std_ulogic := 'U'; TCK : IN std_ulogic := 'U'; Q0 : OUT std_ulogic := 'U'; Q1 : OUT std_ulogic := 'U'; Q2 : OUT std_ulogic := 'U'; Q3 : OUT std_ulogic := 'U'; Q4 : OUT std_ulogic := 'U'; Q5 : OUT std_ulogic := 'U'; Q6 : OUT std_ulogic := 'U'; Q7 : OUT std_ulogic := 'U'; Q8 : OUT std_ulogic := 'U'; Q9 : OUT std_ulogic := 'U'; Q10 : OUT std_ulogic := 'U'; Q11 : OUT std_ulogic := 'U'; Q12 : OUT std_ulogic := 'U'; Q13 : OUT std_ulogic := 'U'; Q14 : OUT std_ulogic := 'U'; Q15 : OUT std_ulogic := 'U'; Q16 : OUT std_ulogic := 'U'; Q17 : OUT std_ulogic := 'U'; Q18 : OUT std_ulogic := 'U'; Q19 : OUT std_ulogic := 'U'; Q20 : OUT std_ulogic := 'U'; Q21 : OUT std_ulogic := 'U'; Q22 : OUT std_ulogic := 'U'; Q23 : OUT std_ulogic := 'U'; Q24 : OUT std_ulogic := 'U'; Q25 : OUT std_ulogic := 'U'; Q26 : OUT std_ulogic := 'U'; Q27 : OUT std_ulogic := 'U'; Q28 : OUT std_ulogic := 'U'; Q29 : OUT std_ulogic := 'U'; Q30 : OUT std_ulogic := 'U'; Q31 : OUT std_ulogic := 'U'; Q32 : OUT std_ulogic := 'U'; Q33 : OUT std_ulogic := 'U'; Q34 : OUT std_ulogic := 'U'; Q35 : OUT std_ulogic := 'U'; CQ : OUT std_ulogic := 'U'; CQNeg : OUT std_ulogic := 'U'; TDO : OUT std_ulogic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of mt54w512h36 : ENTITY IS TRUE;END mt54w512h36;---------------------------------------------------------------------------------- ARCHITECTURE DECLARATION--------------------------------------------------------------------------------ARCHITECTURE vhdl_behavioral of mt54w512h36 IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; CONSTANT partID : STRING := "mt54w512h36";-- two banks(A and B), each has 2^18 (=262144)locations CONSTANT TotalLOC : NATURAL := 262143; CONSTANT MaxData : NATURAL := 511; CONSTANT HiAbit : NATURAL := 17; CONSTANT HiDbit : NATURAL := 8;⌨️ 快捷键说明
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