hm5113805f.vhd

vhdl cod for ram.For sp3e

        END IF;
    END PROCESS Check_delay_to_Din;

    PROCESS(tOED_in)
    BEGIN
        IF rising_edge(tOED_in) THEN
            tOED_out <= '1' AFTER tdevice_tOED, '0' AFTER tdevice_tOED + 1 ns;
        END IF;
    END PROCESS;

    -- checker for tRWD and tRCHR
    Checker : PROCESS(RASNeg, WENeg)
    BEGIN
        IF falling_edge(RASNeg) THEN
            tRWD_in <= '1', '0' AFTER 1 ns;
            tRCHR_in <= '1','0' AFTER 1 ns;
        END IF;

        IF falling_edge(WENeg) THEN
            ASSERT NOT read_entered OR tRWD_out = '1' OR CASNeg = '1'
                REPORT "Not elapsed tRWD time from RASNeg to WENeg " &
                        "during read modify write cycle"
                SEVERITY WARNING;

           ASSERT NOT read_entered OR tRCHR_out = '1' OR CASNeg = '0'
                REPORT "Not elapsed tRCHR time from RASNeg to WENeg"
                SEVERITY WARNING;
        END IF;
    END PROCESS Checker;

    -- checker for tRASMAX
    TRASMAX_proc : PROCESS(RASNeg)
    BEGIN
        IF RASNeg = '0' THEN
            TRASMAX_in <= '1', '0' AFTER 1 ns;
        END IF;

        IF (RASNeg = '1') AND (NOT page_mode) AND (TRASMAX_out = '1') THEN
            ASSERT FALSE
                REPORT "Pulse width low of RAS# is longer than tRAS max value"
                SEVERITY warning;
        END IF;
    END PROCESS TRASMAX_proc;

    -- checker for tRASPMAX
    TRASPMAX_proc : PROCESS(RASNeg)
    BEGIN
        IF RASNeg = '0' THEN
            TRASPMAX_in <= '1', '0' AFTER 1 ns;
        END IF;

        IF (RASNeg = '1') AND page_mode AND (TRASPMAX_out = '1') THEN
            ASSERT FALSE
                REPORT "Pulse width low of RAS# is longer than tRASP max value"
                SEVERITY warning;
        END IF;
    END PROCESS TRASPMAX_proc;

    -- checker for tCASMAX
    TCASMAX_proc : PROCESS(CASNeg)
    BEGIN
        IF CASNeg = '0' THEN
            TCASMAX_in <= '1', '0' AFTER 1 ns;
        END IF;

        IF (CASNeg = '1') AND (NOT page_mode) AND (TCASMAX_out = '1') THEN
            ASSERT FALSE
                REPORT "Pulse width low of CAS# is longer than tCAS max value"
                SEVERITY warning;
        END IF;
    END PROCESS TCASMAX_proc;

    -- checker for tRAD, tRADMAX
    TRAD_proc : PROCESS(RASNeg, AIn)
    BEGIN
        IF falling_edge(RASNeg) AND CASNeg = '1' THEN
            tRAD_in <= '1', '0' AFTER 1 ns;
            tRADMAX_in <= '1', '0' AFTER 1 ns;
        END IF;

        IF AIn'event AND RASNeg = '0' THEN
            ASSERT tRAD_out = '1'
                REPORT "AIn changed before tRAD elapsed"
                SEVERITY warning;

            ASSERT tRADMAX_out = '0'
                REPORT "AIn didn't change before tRADMAX elapsed"
                SEVERITY warning;
        END IF;
    END PROCESS TRAD_proc;

    -- checker for tRCDMAX
    TRCD_proc : PROCESS(RASNeg, CASNeg)
    BEGIN
        IF falling_edge(RASNeg) AND CASNeg = '1' THEN
            tRCDMAX_in <= '1', '0' AFTER 1 ns;
        END IF;

        IF falling_edge(CASNeg) AND RASNeg = '0' THEN
            ASSERT tRCDMAX_out = '0'
                REPORT "CAS# didn't assert low before tRCDMAX elapsed"
                SEVERITY warning;
        END IF;
    END PROCESS TRCD_proc;

    -- checker for tRWC
    TRWC_proc : PROCESS(RASNeg)
    BEGIN
        IF RASNeg = '0' THEN
            IF (NOW - trwc_time) < tdevice_tRWC AND read_mod_wr THEN
                ASSERT FALSE
                    REPORT "Period of RAS is less than tRWC"
                    SEVERITY warning;
            END IF;
            trwc_time := NOW;
            read_mod_wr := FALSE;
        END IF;

    END PROCESS TRWC_proc;

    PROCESS(TRAD_in)
    BEGIN
        IF rising_edge(TRAD_in) THEN
            TRAD_out <= '0', '1' AFTER tdevice_tRAD + 1 ns;
        END IF;
    END PROCESS;

    PROCESS(TRADMAX_in, CASNeg)
    BEGIN
        IF rising_edge(TRADMAX_in) THEN
            TRADMAX_out <= '0', '1' AFTER tdevice_tRADMAX + 1 ns;
        ELSIF rising_edge(CASNeg) THEN
            TRADMAX_out <= '0';
        END IF;
    END PROCESS;

    PROCESS(TRCDMAX_in, CASNeg)
    BEGIN
        IF rising_edge(TRCDMAX_in) THEN
            TRCDMAX_out <= '0', '1' AFTER tdevice_tRCDMAX + 1 ns;
        ELSIF rising_edge(CASNeg) THEN
            TRCDMAX_out <= '0';
        END IF;
    END PROCESS;

    PROCESS(TRASMAX_in)
    BEGIN
        IF rising_edge(TRASMAX_in) THEN
            TRASMAX_out <= '0', '1' AFTER tdevice_tRASMAX + 1 ns;
        END IF;
    END PROCESS;

    PROCESS(TRASPMAX_in)
    BEGIN
        IF rising_edge(TRASPMAX_in) THEN
            TRASPMAX_out <= '0', '1' AFTER tdevice_tRASPMAX + 1 ns;
        END IF;
    END PROCESS;

    PROCESS(TCASMAX_in)
    BEGIN
        IF rising_edge(TCASMAX_in) THEN
            TCASMAX_out <= '0', '1' AFTER tdevice_tCASMAX + 1 ns;
        END IF;
    END PROCESS;

    PROCESS(tRWD_in)
    BEGIN
        IF rising_edge(tRWD_in) THEN
            tRWD_out <= '0', '1' AFTER tdevice_tRWD + 1 ns;
        END IF;
    END PROCESS;

    PROCESS(tRCHR_in)
    BEGIN
        IF rising_edge(tRCHR_in) THEN
            tRCHR_out <= '0', '1' AFTER tdevice_tRCHR + 1 ns;
        END IF;
    END PROCESS;

    DOutPassThrough : PROCESS(DOut_zd)
        VARIABLE ValidData         : std_logic_vector(7 downto 0);
        VARIABLE CASDQ_negt        : TIME;
        VARIABLE CASDQ_post        : TIME;
        VARIABLE CASDQ_t           : TIME;
        VARIABLE RASDQ_t           : TIME;
        VARIABLE OEDQ_t            : TIME;
        VARIABLE WEDQ_t            : TIME;
        VARIABLE ADDRDQ_t          : TIME;
        VARIABLE after_ADDR        : BOOLEAN;
        VARIABLE after_RAS         : BOOLEAN;
        VARIABLE time_tmp          : TIME;

    BEGIN
       IF DOut_zd(0) /= 'Z' THEN
           OPENLATCH  := TRUE;
           CASDQ_negt := -CASNeg'LAST_EVENT + tpd_CASNeg_IO0_neg_edge(trz0);
           CASDQ_post := -CAS_posedge'LAST_EVENT +
                                             tpd_CASNeg_IO0_pos_edge(trz0);
           RASDQ_t    := -RASNeg'LAST_EVENT + tpd_RASNeg_IO0(trz0);
           OEDQ_t     := -OENeg'LAST_EVENT + tpd_OENeg_IO0(trz0);
           ADDRDQ_t   := -AIn'LAST_EVENT     + tpd_A0_IO0(tr01);

           IF CAS_low THEN
               IF (CASDQ_negt >= CASDQ_post)  AND (CASDQ_negt > 0 ns) THEN
                   CASDQ_t := CASDQ_negt;
                   from_neg_en := TRUE;
               ELSIF (CASDQ_post >= CASDQ_negt)  AND (CASDQ_post > 0 ns) THEN
                   CASDQ_t := CASDQ_post;
                   from_neg_en := FALSE;
               END IF;
           ELSE
               from_neg_en := FALSE;
           END IF;

           FROMCAS   := (CASDQ_t > OEDQ_t)  AND (CASDQ_t > 0 ns);
           FROMOE    := (OEDQ_t >= CASDQ_t) AND (OEDQ_t > 0 ns);
           ValidData := "XXXXXXXX";

           IF (ADDRDQ_t > 0 ns AND ADDRDQ_t > RASDQ_t) THEN
               after_ADDR := TRUE;
               after_RAS := FALSE;
           ELSIF (RASDQ_t > 0 ns AND RASDQ_t > ADDRDQ_t) THEN
               after_ADDR := FALSE;
               after_RAS := TRUE;
           ELSE
               after_ADDR := FALSE;
               after_RAS := FALSE;
           END IF;
           IF (after_ADDR AND
           (((ADDRDQ_t > CASDQ_t) AND FROMCAS) OR
            ((ADDRDQ_t > OEDQ_t) AND FROMOE))) THEN
               DOut_Pass <= ValidData,
                            DOut_zd AFTER ADDRDQ_t;
           ELSIF ((RASDQ_t > CASDQ_t) AND FROMCAS) OR
            ((RASDQ_t > OEDQ_t) AND FROMOE) THEN
               FROMRAS := TRUE;
               FROMOE := FALSE;
               FROMCAS := FALSE;
               DOut_Pass <= DOut_zd;
           ELSE
               DOut_Pass <= DOut_zd;
           END IF;
       ELSE
           CASDQ_t := -CASNeg'LAST_EVENT + tpd_CASNeg_IO0_neg_edge(tr0z);
           RASDQ_t := -RASNeg'LAST_EVENT + tpd_RASNeg_IO0(tr0z);
           OEDQ_t := -OENeg'LAST_EVENT + tpd_OENeg_IO0(tr0z);
           WEDQ_t := -WENeg'LAST_EVENT + tpd_WENeg_IO0(tr0z);

           FROMRAS := ((RASDQ_t <= WEDQ_t AND WEDQ_t >= 0 ns) OR (
                  RASDQ_t > WEDQ_t AND WEDQ_t < 0 ns)) AND (RASDQ_t > 0 ns) AND
                  ((RASDQ_t <= OEDQ_t AND OEDQ_t >= 0 ns) OR
                  (RASDQ_t > OEDQ_t AND OEDQ_t < 0 ns)) AND
                  ((RASDQ_t <= CASDQ_t AND CASDQ_t >= 0 ns) OR
                   (RASDQ_t > CASDQ_t AND CASDQ_t < 0 ns)) AND end_cycle;
           FROMOE := ((OEDQ_t <= WEDQ_t AND WEDQ_t >= 0 ns) OR (
                  OEDQ_t > WEDQ_t AND WEDQ_t < 0 ns)) AND (OEDQ_t > 0 ns) AND
                  ((OEDQ_t <= RASDQ_t AND RASDQ_t >= 0 ns) OR
                  (OEDQ_t > RASDQ_t AND RASDQ_t < 0 ns)) AND
                  ((OEDQ_t <= CASDQ_t AND CASDQ_t >= 0 ns) OR
                   (OEDQ_t > CASDQ_t AND CASDQ_t < 0 ns));
           FROMCAS :=((CASDQ_t <= WEDQ_t AND WEDQ_t >= 0 ns) OR (
                  CASDQ_t > WEDQ_t AND WEDQ_t < 0 ns)) AND (CASDQ_t > 0 ns) AND
                  ((CASDQ_t <= OEDQ_t AND OEDQ_t >= 0 ns) OR
                  (CASDQ_t > OEDQ_t AND OEDQ_t < 0 ns)) AND
                  ((CASDQ_t <= RASDQ_t AND RASDQ_t >= 0 ns) OR
                   (CASDQ_t > RASDQ_t AND RASDQ_t < 0 ns)) AND end_cycle;
           DOut_Pass <= DOut_zd;
           OPENLATCH := FALSE;
       END IF;
   END PROCESS DOutPassThrough;

    ---------------------------------------------------------------------------
    -- Path Delay Section
    ---------------------------------------------------------------------------
    D_Out_PathDelay_Gen : FOR i IN 0 TO 7 GENERATE
    PROCESS(DOut_Pass(i))
        VARIABLE D0_GlitchData     : VitalGlitchDataType;

        BEGIN
            VitalPathDelay01Z(
                OutSignal           => DOut(i),
                OutSignalName       => "DOut",
                OutTemp             => DOut_Pass(i),
                GlitchData          => D0_GlitchData,
                Mode                => VitalTransport,
                Paths               => (
                0 => (InputChangeTime => CASNeg'LAST_EVENT,
                      PathDelay       => tpd_CASNeg_IO0_neg_edge,
                      PathCondition   => (NOT OPENLATCH AND FROMCAS) OR
                                         (OPENLATCH AND FROMCAS AND
                                          from_neg_en)),
                1 => (InputChangeTime => CAS_posedge'LAST_EVENT,
                      PathDelay       => tpd_CASNeg_IO0_pos_edge,
                      PathCondition   => (OPENLATCH AND FROMCAS AND
                                         (NOT from_neg_en) AND
                                         (CAS_low))),
                2 => (InputChangeTime => RASNeg'LAST_EVENT,
                      PathDelay       => tpd_RASNeg_IO0,
                      PathCondition   => (NOT OPENLATCH AND FROMRAS) OR
                                         (OPENLATCH AND FROMRAS)),
                3 => (InputChangeTime => OENeg'LAST_EVENT,
                      PathDelay       => tpd_OENeg_IO0,
                      PathCondition   => (NOT OPENLATCH AND FROMOE) OR
                                         (OPENLATCH AND FROMOE)),
                4 => (InputChangeTime => AIn'LAST_EVENT,
                      PathDelay       => VitalExtendToFillDelay(tpd_A0_IO0),
                      PathCondition   => (NOT FROMOE) AND (NOT FROMCAS) AND
                                          (NOT FROMRAS)),
                5 => (InputChangeTime => WENeg'LAST_EVENT,
                      PathDelay       => VitalExtendToFillDelay(tpd_WENeg_IO0),
                      PathCondition   => (NOT FROMOE) AND (NOT FROMCAS) AND
                                         (NOT FROMRAS) AND NOT OPENLATCH)
                )
            );
        END PROCESS;
   END GENERATE D_Out_PathDelay_Gen;

    default: PROCESS
        -- Text file input variables
        FILE mem_file : text IS mem_file_name;

        VARIABLE ind  : natural := 0;
        VARIABLE buf  : line;

    BEGIN
        -- Preload Control
        ------------------------------------------------------------------------
        -- File Read Section
        ------------------------------------------------------------------------
        ------------------------------------------------------------------------
        ----- hm5113805f memory preload file format ----------------------------
        --------------------------------------------------