hm5113805f.vhd

vhdl cod for ram.For sp3e

            PeriodData      => PD_WENeg,
            Violation       => Pviol_WENeg
        );

        -- PulseWidth Check for OENeg
        VitalPeriodPulseCheck (
            TestSignal      => OENeg,
            TestSignalName  => "OENeg",
            PulseWidthHigh  => tpw_OENeg_posedge,
            CheckEnabled    => page_mode = TRUE,
            HeaderMsg       => InstancePath & PartID,
            PeriodData      => PD_OENeg,
            Violation       => Pviol_OENeg
        );

        Violation := Tviol_IO0_WENeg            OR
                     Tviol_IO0_CASNeg           OR
                     Tviol_A0_CASNeg_s          OR
                     Tviol_A0_CASNeg_h          OR
                     Tviol_A0_RASNeg_s          OR
                     Tviol_A0_RASNeg_h          OR
                     Tviol_A0_WENeg             OR
                     Tviol_OENeg_WENeg          OR
                     Tviol_OENeg_CASNeg         OR
                     Tviol_CASNeg_OENeg         OR
                     Tviol_CASNeg_WENeg         OR
                     Tviol_CASNeg_WENeg_1       OR
                     Tviol_RASNeg_CASNeg        OR
                     Tviol_RASNeg_CASNeg_1      OR
                     Tviol_RASNeg_CASNeg_2      OR
                     Tviol_RASNeg_CASNeg_3      OR
                     Tviol_CASNeg_RASNeg        OR
                     Tviol_CASNeg_RASNeg_1      OR
                     Tviol_CASNeg_RASNeg_2      OR
                     Tviol_WENeg_CASNeg         OR
                     Tviol_WENeg_CASNeg_1       OR
                     Tviol_WENeg_CASNeg_2       OR
                     Tviol_WENeg_RASNeg         OR
                     Tviol_RASNeg_WENeg         OR
                     Pviol_RASNeg               OR
                     Pviol_CASNeg               OR
                     Pviol_CASNeg_rd            OR
                     Pviol_CASNeg_rd_mod_wr    OR
                     Pviol_OENeg                OR
                     Pviol_WENeg;

        Viol <= Violation;

        ASSERT Violation = '0'
            REPORT InstancePath & partID & ": simulation may be" &
                    " inaccurate due to timing violations"
            SEVERITY warning;
    END IF;

    END PROCESS VITALBehaviour;

    ref_decode : PROCESS(CASNeg, RASNeg)
    VARIABLE RAS_ONLY_REF : BOOLEAN;
    VARIABLE CAS_BEFORE_RAS_REF : BOOLEAN;
    BEGIN
        IF falling_edge(RASNeg) AND CASNeg = '1' THEN
            RAS_ONLY_REF := TRUE;
        ELSIF rising_edge(RASNeg) AND CASNeg = '1' AND RAS_ONLY_REF THEN
            RAS_ONLY_REF := FALSE;
            Init_change <= '1', '0' AFTER 1 ns;
        ELSIF falling_edge(RASNeg) AND CASNeg = '0' AND WENeg = '1' THEN
            CAS_BEFORE_RAS_REF := TRUE;
        ELSIF rising_edge(RASNeg) AND CAS_BEFORE_RAS_REF THEN
            CAS_BEFORE_RAS_REF := FALSE;
            Init_change <= '1', '0' AFTER 1 ns;
        END IF;
    END PROCESS ref_decode;

    StateGen : PROCESS(Init_change)
    BEGIN
        CASE curr_init_state IS
            WHEN init0 =>
                IF (PoweredUp = '1') AND (Init_change = '1') THEN
                    next_init_state <= init1;
                ELSE
                    next_init_state <= init0;
                END IF;

            WHEN init1 =>
                IF Init_change = '1' THEN
                    next_init_state <= init2;
                ELSE
                    next_init_state <= init1;
                END IF;

            WHEN init2 =>
                IF Init_change = '1' THEN
                    next_init_state <= init3;
                ELSE
                    next_init_state <= init2;
                END IF;

            WHEN init3 =>
                IF Init_change = '1' THEN
                    next_init_state <= init4;
                ELSE
                    next_init_state <= init3;
                END IF;

            WHEN init4 =>
                IF Init_change = '1' THEN
                    next_init_state <= init5;
                ELSE
                    next_init_state <= init4;
                END IF;

            WHEN init5 =>
                IF Init_change = '1' THEN
                    next_init_state <= init6;
                ELSE
                    next_init_state <= init5;
                END IF;

            WHEN init6 =>
                IF Init_change = '1' THEN
                    next_init_state <= init7;
                ELSE
                    next_init_state <= init6;
                END IF;

            WHEN init7 =>
                IF Init_change = '1' THEN
                    next_init_state <= init8;
                ELSE
                    next_init_state <= init7;
                END IF;

            WHEN init8 =>
                        NULL;

        END CASE;
    END PROCESS StateGen;

    StateTransition : PROCESS(next_init_state)
    BEGIN
        IF PoweredUp = '1' THEN
            curr_init_state <= next_init_state;
        ELSE
            curr_init_state <= init0;
        END IF;
    END PROCESS StateTransition;

    Functionality : PROCESS(curr_init_state)
    BEGIN
        CASE curr_init_state IS
            WHEN init0 =>
                       NULL;

            WHEN init1 =>
                       NULL;

            WHEN init2 =>
                       NULL;

            WHEN init3 =>
                       NULL;

            WHEN init4 =>
                       NULL;

            WHEN init5 =>
                       NULL;

            WHEN init6 =>
                       NULL;

            WHEN init7 =>
                       NULL;

            WHEN init8 =>
                Initialized <= '1';

        END CASE;
    END PROCESS Functionality;

    -- check if early or delayed write cycle
    PROCESS (CASNeg, WENeg)
    BEGIN
        IF RASNeg = '0' AND falling_edge(CASNeg) AND WENeg = '1' THEN
            twcs_count := FALSE;
        ELSIF RASNeg = '0' AND ((falling_edge(WENeg) AND CASNeg = '1') OR
            (falling_edge(CASNeg) AND falling_edge(WENeg))) THEN
            twcs_count := TRUE;
        END IF;

    END PROCESS;

    write_dc: PROCESS (WENeg, CASNeg, OENeg, RASNeg)
    BEGIN
        IF Initialized = '1' THEN
            IF (WENeg = '0') AND (CASNeg = '0') AND (RASNeg = '0') AND
              ((OENeg = '1' AND NOT twcs_count) OR twcs_count) THEN
                write <= '1';
            ELSE
                write <= '0';
            END IF;

            IF (WENeg = '1') AND (CASNeg = '0' AND RASNeg = '0') AND
              (OENeg = '0') THEN
                read <= '1';
            ELSE
                read <= '0';
            END IF;
        ELSE
            read <= '0';
            write <= '0';
        END IF;

    END PROCESS write_dc;

    ---------------------------------------------------------------------------
    --Latch address on falling edge of RAS# and CAS#
    --Latches data on falling edge of WE# or CAS# what ever comes later
    ---------------------------------------------------------------------------
    BusCycleDecode : PROCESS(AIn, Din, write, WENeg, CASNeg, RASNeg, OENeg)

        VARIABLE Row   : NATURAL RANGE 0 TO RowSize;
        VARIABLE Column : NATURAL RANGE 0 TO ColSize;
    BEGIN
        IF Initialized = '1' THEN
            IF (falling_edge(RASNeg) AND CASNeg= '1') THEN
                Row := to_nat(AIn(11 downto 0));
            ELSIF (falling_edge(CASNeg) AND RASNeg = '0') THEN
                Column := to_nat(AIn(11 downto 0));
                Mem_addr   := Row*(RowSize+1) + Column;
                Mem_address <= Mem_addr;
            ELSIF rising_edge(write) THEN
                Mem(Mem_addr) := to_nat(Din);
                D_tmp <= to_nat(Din);
            END IF;
        END IF;

    END PROCESS BusCycleDecode;

    page_read_modify_write : PROCESS(CASNeg, RASNeg,RAS_posedge, WENeg, OENeg)
    VARIABLE cnt : NATURAL :=0;
    VARIABLE read_wr_possible : BOOLEAN;
    BEGIN
        IF falling_edge(RASNeg) or rising_edge(RAS_posedge) THEN
            read_wr_possible := FALSE;
            read_entered := FALSE;
            page_mode := FALSE;
            cnt := 0;
        END IF;

        IF falling_edge(CASNeg) AND RASNeg = '0' THEN
            read_wr_possible := TRUE;
            read_entered := FALSE;
            read_mod_wr := FALSE;
            cnt := cnt + 1;
        ELSIF rising_edge(CASNeg) THEN
            read_wr_possible := FALSE;
        END IF;

        IF rising_edge(OENeg) AND CASNeg = '0' AND read_wr_possible THEN
            read_entered := TRUE;
        ELSIF falling_edge(WENeg) AND CASNeg = '0' AND read_entered THEN
            read_mod_wr := TRUE;
        ELSIF falling_edge(CASNeg) AND (RASNeg = '0' AND cnt > 1) THEN
            page_mode := TRUE;
        END IF;

    END PROCESS page_read_modify_write;

    read_proc : PROCESS(CASNeg, RASNeg, OENeg, WENeg, read)
    BEGIN
        oe:= rising_edge(read) OR (read = '1');
        IF oe THEN
            IF Mem(Mem_addr) = -1 THEN
                DOut_zd <= (OTHERS=>'X');
            ELSE
                DOut_zd <= to_slv(Mem(Mem_addr),8);
            END IF;
        END IF;

       IF OENeg = '1' OR WENeg = '0' OR (RASNeg = '1' AND CASNeg = '1') THEN
           DOut_zd <= (OTHERS=>'Z');
       END IF;

       IF (RASNeg = '1' AND CASNeg = '1') THEN
           end_cycle := TRUE;
       ELSE
           end_cycle := FALSE;
       END IF;

    END PROCESS read_proc;

    -- generate signal CAS_posedge and variable CAS_low to provide
    -- tCAP time passed when reading
    gen_CAS_posedge : PROCESS(CASNeg)
    BEGIN
        IF CASNeg = '0' THEN
            CAS_low := TRUE;
        ELSE
            CAS_low := FALSE;
        END IF;

        IF CASNeg = '1' THEN
            CAS_posedge <= NOT CAS_posedge;
        ELSE
            CAS_posedge <= CAS_posedge;
        END IF;
    END PROCESS gen_CAS_posedge;

    gen_RAS_posedge : PROCESS(RASNeg)
    BEGIN
        IF RASNeg = '1' THEN
            RAS_posedge <= '0', '1' AFTER 1 ns;
        ELSE
            RAS_posedge <= '0';
        END IF;
    END PROCESS gen_RAS_posedge;

    -- checker for tCDD, tRDD, tOED, tWED
    Check_delay_to_Din : PROCESS(CASNeg, RASNeg, OENeg, WENeg, Din, tOED_out)
    BEGIN
        IF (rising_edge(OENeg) OR rising_edge(CASNeg) OR rising_edge(RASNeg) OR
           falling_edge(WENeg)) AND Din(0) /= '0' AND Din(0) /= '1' THEN
            tOED_in <= '1';
        ELSIF tOED_in = '1' AND tOED_out = '0' AND
          (Din(0) = '0' OR Din(0) = '1') THEN
            ASSERT FALSE
                REPORT "During 15 ns Din should be Hi-Z"
                SEVERITY warning;
        END IF;

        IF falling_edge(tOED_out) THEN
            tOED_in <= '0';