hm5113805f.vhd

vhdl cod for ram.For sp3e

        w_23 : VitalWireDelay (IO6_ipd, IO6, tipd_IO6);
        w_24 : VitalWireDelay (IO7_ipd, IO7, tipd_IO7);
    END BLOCK;

    CASNeg_nwv     <= To_UX01(CASNeg_ipd);
    RASNeg_nwv     <= To_UX01(RASNeg_ipd);
    WENeg_nwv      <= To_UX01(WENeg_ipd);
    OENeg_nwv      <= To_UX01(OENeg_ipd);
    A0_nwv         <= To_UX01(A0_ipd);
    A1_nwv         <= To_UX01(A1_ipd);
    A2_nwv         <= To_UX01(A2_ipd);
    A3_nwv         <= To_UX01(A3_ipd);
    A4_nwv         <= To_UX01(A4_ipd);
    A5_nwv         <= To_UX01(A5_ipd);
    A6_nwv         <= To_UX01(A6_ipd);
    A7_nwv         <= To_UX01(A7_ipd);
    A8_nwv         <= To_UX01(A8_ipd);
    A9_nwv         <= To_UX01(A9_ipd);
    A10_nwv        <= To_UX01(A10_ipd);
    A11_nwv        <= To_UX01(A11_ipd);
    IO0_nwv        <= To_UX01(IO0_ipd);
    IO1_nwv        <= To_UX01(IO1_ipd);
    IO2_nwv        <= To_UX01(IO2_ipd);
    IO3_nwv        <= To_UX01(IO3_ipd);
    IO4_nwv        <= To_UX01(IO4_ipd);
    IO5_nwv        <= To_UX01(IO5_ipd);
    IO6_nwv        <= To_UX01(IO6_ipd);
    IO7_nwv        <= To_UX01(IO7_ipd);

    ----------------------------------------------------------------------------
    -- Main Behavior Block
    ----------------------------------------------------------------------------
    Behavior: BLOCK

        PORT (
            CASNeg         : IN    std_ulogic := 'U';
            RASNeg         : IN    std_ulogic := 'U';
            WENeg          : IN    std_ulogic := 'U';
            OENeg          : IN    std_ulogic := 'U';
            AIn            : IN    std_logic_vector(11 DOWNTO 0) :=
                                               (OTHERS => 'U');
            DIn           : IN    std_logic_vector(7 DOWNTO 0) :=
                                               (OTHERS => 'U');
            DOut          : OUT   std_ulogic_vector(7 DOWNTO 0) :=
                                               (OTHERS => 'Z')
        );

        PORT MAP (
            CASNeg    => CASNeg_nwv,
            RASNeg    => RASNeg_nwv,
            WENeg     => WENeg_nwv,
            OENeg     => OENeg_nwv,
            AIn(0)    => A0_nwv,
            AIn(1)    => A1_nwv,
            AIn(2)    => A2_nwv,
            AIn(3)    => A3_nwv,
            AIn(4)    => A4_nwv,
            AIn(5)    => A5_nwv,
            AIn(6)    => A6_nwv,
            AIn(7)    => A7_nwv,
            AIn(8)    => A8_nwv,
            AIn(9)    => A9_nwv,
            AIn(10)   => A10_nwv,
            AIn(11)   => A11_nwv,
            DIn(0)   => IO0_nwv,
            DIn(1)   => IO1_nwv,
            DIn(2)   => IO2_nwv,
            DIn(3)   => IO3_nwv,
            DIn(4)   => IO4_nwv,
            DIn(5)   => IO5_nwv,
            DIn(6)   => IO6_nwv,
            DIn(7)   => IO7_nwv,
            DOut(0)  => IO0,
            DOut(1)  => IO1,
            DOut(2)  => IO2,
            DOut(3)  => IO3,
            DOut(4)  => IO4,
            DOut(5)  => IO5,
            DOut(6)  => IO6,
            DOut(7)  => IO7
        );

        --memory definition
        TYPE MemStore IS ARRAY (0 TO MemSize) OF integer RANGE -2 TO MaxData;
        SHARED VARIABLE Mem    : MemStore;

        -- states during initialization
        TYPE State_type IS (init0, init1, init2, init3, init4, init5,
                            init6, init7, init8);
        SIGNAL curr_init_state : State_type := init0;
        SIGNAL next_init_state : State_type := init0;

        -- powerup
        SIGNAL PoweredUp        : std_logic := '0';

        -- initialization
        SIGNAL Initialized     : std_logic := '0';

        --zero delay signals
        SIGNAL DOut_zd          : std_logic_vector(7 downto 0):=(OTHERS=>'Z');
        SIGNAL DOut_Pass        : std_logic_vector(7 downto 0):=(OTHERS=>'Z');

        SIGNAL D_tmp            : NATURAL RANGE 0 TO MaxData;

        SIGNAL Mem_address      : NATURAL RANGE 0 TO MemSize;

        --Command Register
        SIGNAL write            : std_logic := '0';
        SIGNAL read             : std_logic := '0';

        SIGNAL Init_change      : std_logic := '0';

        -- has value '1' for 1 ns when CAS# is high
        SIGNAL CAS_posedge      : std_logic := '0';

        SIGNAL RAS_posedge      : std_logic := '0';

        SHARED VARIABLE CAS_low : BOOLEAN;

        SHARED VARIABLE from_neg_en : BOOLEAN;

        SHARED VARIABLE page_mode : BOOLEAN;

        SHARED VARIABLE oe     : BOOLEAN;

        SHARED VARIABLE trwc_time : time := 0 ns;

        SHARED VARIABLE read_mod_wr : BOOLEAN;

        SHARED VARIABLE Mem_addr : NATURAL RANGE 0 TO MemSize;

        SHARED VARIABLE read_entered : BOOLEAN;

        -- set to TRUE when early write cycle
        SHARED VARIABLE twcs_count : BOOLEAN;

        SHARED VARIABLE end_cycle  : BOOLEAN;

        -- Access time variables
        SHARED VARIABLE OPENLATCH    : BOOLEAN;
        SHARED VARIABLE FROMCAS      : BOOLEAN;
        SHARED VARIABLE FROMOE       : BOOLEAN;
        SHARED VARIABLE FROMRAS      : BOOLEAN;
        SHARED VARIABLE FROMWE       : BOOLEAN;

        -- timing check violation
        SIGNAL Viol : X01 := '0';

    BEGIN

    ----------------------------------------------------------------------------
    --Power Up time 200 us;
    ---------------------------------------------------------------------------
    PoweredUp <= '1' AFTER 200 us;

    ----------------------------------------------------------------------------
    -- Main Behavior Process
    ----------------------------------------------------------------------------
    VITALBehaviour: PROCESS(DIn, RASNeg, CASNeg,
                            WENeg, OEneg, AIn)

        -- Timing Check Variables
        VARIABLE Tviol_IO0_WENeg          : X01 := '0';
        VARIABLE TD_IO0_WENeg             : VitalTimingDataType;

        VARIABLE Tviol_IO0_CASNeg         : X01 := '0';
        VARIABLE TD_IO0_CASNeg            : VitalTimingDataType;

        VARIABLE Tviol_A0_CASNeg_s        : X01 := '0';
        VARIABLE TD_A0_CASNeg_s           : VitalTimingDataType;

        VARIABLE Tviol_A0_CASNeg_h        : X01 := '0';
        VARIABLE TD_A0_CASNeg_h           : VitalTimingDataType;

        VARIABLE Tviol_A0_RASNeg_s        : X01 := '0';
        VARIABLE TD_A0_RASNeg_s           : VitalTimingDataType;

        VARIABLE Tviol_A0_RASNeg_h        : X01 := '0';
        VARIABLE TD_A0_RASNeg_h           : VitalTimingDataType;

        VARIABLE Tviol_A0_WENeg           : X01 := '0';
        VARIABLE TD_A0_WENeg              : VitalTimingDataType;

        VARIABLE Tviol_OENeg_WENeg        : X01 := '0';
        VARIABLE TD_OENeg_WENeg           : VitalTimingDataType;

        VARIABLE Tviol_OENeg_CASNeg       : X01 := '0';
        VARIABLE TD_OENeg_CASNeg          : VitalTimingDataType;

        VARIABLE Tviol_CASNeg_OENeg       : X01 := '0';
        VARIABLE TD_CASNeg_OENeg          : VitalTimingDataType;

        VARIABLE Tviol_CASNeg_WENeg       : X01 := '0';
        VARIABLE TD_CASNeg_WENeg          : VitalTimingDataType;

        VARIABLE Tviol_CASNeg_WENeg_1     : X01 := '0';
        VARIABLE TD_CASNeg_WENeg_1        : VitalTimingDataType;

        VARIABLE Tviol_RASNeg_CASNeg      : X01 := '0';
        VARIABLE TD_RASNeg_CASNeg         : VitalTimingDataType;

        VARIABLE Tviol_RASNeg_CASNeg_1    : X01 := '0';
        VARIABLE TD_RASNeg_CASNeg_1       : VitalTimingDataType;

        VARIABLE Tviol_RASNeg_CASNeg_2    : X01 := '0';
        VARIABLE TD_RASNeg_CASNeg_2       : VitalTimingDataType;

        VARIABLE Tviol_RASNeg_CASNeg_3    : X01 := '0';
        VARIABLE TD_RASNeg_CASNeg_3       : VitalTimingDataType;

        VARIABLE Tviol_CASNeg_RASNeg      : X01 := '0';
        VARIABLE TD_CASNeg_RASNeg         : VitalTimingDataType;

        VARIABLE Tviol_CASNeg_RASNeg_1    : X01 := '0';
        VARIABLE TD_CASNeg_RASNeg_1       : VitalTimingDataType;

        VARIABLE Tviol_CASNeg_RASNeg_2    : X01 := '0';
        VARIABLE TD_CASNeg_RASNeg_2       : VitalTimingDataType;

        VARIABLE Tviol_WENeg_CASNeg       : X01 := '0';
        VARIABLE TD_WENeg_CASNeg          : VitalTimingDataType;

        VARIABLE Tviol_WENeg_CASNeg_1     : X01 := '0';
        VARIABLE TD_WENeg_CASNeg_1        : VitalTimingDataType;

        VARIABLE Tviol_WENeg_CASNeg_2     : X01 := '0';
        VARIABLE TD_WENeg_CASNeg_2        : VitalTimingDataType;

        VARIABLE Tviol_WENeg_RASNeg       : X01 := '0';
        VARIABLE TD_WENeg_RASNeg          : VitalTimingDataType;

        VARIABLE Tviol_RASNeg_WENeg       : X01 := '0';
        VARIABLE TD_RASNeg_WENeg          : VitalTimingDataType;

        VARIABLE Pviol_RASNeg     : X01 := '0';
        VARIABLE PD_RASNeg        : VitalPeriodDataType := VitalPeriodDataInit;

        VARIABLE Pviol_CASNeg     : X01 := '0';
        VARIABLE PD_CASNeg        : VitalPeriodDataType := VitalPeriodDataInit;

        VARIABLE Pviol_CASNeg_rd  : X01 := '0';
        VARIABLE PD_CASNeg_rd     : VitalPeriodDataType := VitalPeriodDataInit;

        VARIABLE Pviol_CASNeg_rd_mod_wr   : X01 := '0';
        VARIABLE PD_CASNeg_rd_mod_wr : VitalPeriodDataType
                                                         := VitalPeriodDataInit;

        VARIABLE Pviol_WENeg       : X01 := '0';
        VARIABLE PD_WENeg          : VitalPeriodDataType
                                                         := VitalPeriodDataInit;

        VARIABLE Pviol_OENeg       : X01 := '0';
        VARIABLE PD_OENeg          : VitalPeriodDataType
                                                         := VitalPeriodDataInit;

        VARIABLE Violation         : X01 := '0';

    BEGIN

    ----------------------------------------------------------------------------
    -- Timing Check Section
    ----------------------------------------------------------------------------
    IF (TimingChecksOn) THEN

        -- Setup/Hold Check between DIn and WENeg
        VitalSetupHoldCheck (
            TestSignal      => DIn,
            TestSignalName  => "DIn",
            RefSignal       => WENeg,
            RefSignalName   => "WENeg",
            SetupHigh       => tsetup_IO0_WENeg,
            SetupLow        => tsetup_IO0_WENeg,
            HoldHigh        => thold_IO0_WENeg,
            HoldLow         => thold_IO0_WENeg,
            CheckEnabled    => CASNeg = '0' AND OENeg = '1',
            RefTransition   => '\',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_IO0_WENeg,
            Violation       => Tviol_IO0_WENeg
        );

        -- Setup/Hold Check between DIn and CASNeg
        VitalSetupHoldCheck (
            TestSignal      => DIn,
            TestSignalName  => "DIn",
            RefSignal       => CASNeg,
            RefSignalName   => "CASNeg",
            SetupHigh       => tsetup_IO0_CASNeg,
            SetupLow        => tsetup_IO0_CASNeg,
            HoldHigh        => thold_IO0_CASNeg,
            HoldLow         => thold_IO0_CASNeg,
            CheckEnabled    => WENeg = '0' AND OENeg = '1',
            RefTransition   => '\',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_IO0_CASNeg,
            Violation       => Tviol_IO0_CASNeg
        );

        -- Setup/Hold Check between RASNeg and CASNeg
        VitalSetupHoldCheck (
            TestSignal      => RASNeg,
            TestSignalName  => "RASNeg",
            RefSignal       => CASNeg,
            RefSignalName   => "CASNeg",
            SetupLow        => tsetup_RASNeg_CASNeg_read_noedge_posedge, --tcsh
            CheckEnabled    => TRUE,
            RefTransition   => '/',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_RASNeg_CASNeg,
            Violation       => Tviol_RASNeg_CASNeg
        );

        -- Setup/Hold Check between RASNeg and CASNeg
        VitalSetupHoldCheck (
            TestSignal      => RASNeg,
            TestSignalName  => "RASNeg",
            RefSignal       => CASNeg,
            RefSignalName   => "CASNeg",
            SetupLow       => tsetup_RASNeg_CASNeg_read1_noedge_negedge,-- trcd
            HoldLow        => thold_RASNeg_CASNeg_read_noedge_negedge,  -- trsh
            CheckEnabled    => TRUE,
            RefTransition   => '\',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_RASNeg_CASNeg_1,
            Violation       => Tviol_RASNeg_CASNeg_1
        );

        -- Setup/Hold Check between CASNeg and RASNeg
        VitalSetupHoldCheck (
            TestSignal      => CASNeg,
            TestSignalName  => "CASNeg",
            RefSignal       => RASNeg,
            RefSignalName   => "RASNeg",        -- trpc