hm5113805f.vhd

vhdl cod for ram.For sp3e

--------------------------------------------------------------------------------
--  File Name: hm5113805f.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 2007 Free Model Foundry; http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--  MODIFICATION HISTORY:
--
--  version: |  author:         | mod date: | changes made:
--    V1.0     S.Janevski        07 Aug 24   Initial release
--
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
--
--  Library:    RAM
--  Technology: CMOS
--  Part:       HM5113805F
--
--  Description: 128M (16 Mword x 8) EDO DRAM
--------------------------------------------------------------------------------

LIBRARY IEEE;      USE IEEE.std_logic_1164.ALL;
                   USE IEEE.VITAL_timing.ALL;
                   USE IEEE.VITAL_primitives.ALL;
                   USE STD.textio.ALL;

LIBRARY FMF;       USE FMF.gen_utils.ALL;
                   USE FMF.conversions.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY hm5113805f IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_CASNeg       : VitalDelayType01 := VitalZeroDelay01;
        tipd_RASNeg       : VitalDelayType01 := VitalZeroDelay01;
        tipd_WENeg        : VitalDelayType01 := VitalZeroDelay01;
        tipd_OENeg        : VitalDelayType01 := VitalZeroDelay01;
        tipd_A0           : VitalDelayType01 := VitalZeroDelay01;
        tipd_A1           : VitalDelayType01 := VitalZeroDelay01;
        tipd_A2           : VitalDelayType01 := VitalZeroDelay01;
        tipd_A3           : VitalDelayType01 := VitalZeroDelay01;
        tipd_A4           : VitalDelayType01 := VitalZeroDelay01;
        tipd_A5           : VitalDelayType01 := VitalZeroDelay01;
        tipd_A6           : VitalDelayType01 := VitalZeroDelay01;
        tipd_A7           : VitalDelayType01 := VitalZeroDelay01;
        tipd_A8           : VitalDelayType01 := VitalZeroDelay01;
        tipd_A9           : VitalDelayType01 := VitalZeroDelay01;
        tipd_A10          : VitalDelayType01 := VitalZeroDelay01;
        tipd_A11          : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO0          : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO1          : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO2          : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO3          : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO4          : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO5          : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO6          : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO7          : VitalDelayType01 := VitalZeroDelay01;

        -- tpd delays
        tpd_CASNeg_IO0_neg_edge : VitalDelayType01Z := UnitDelay01Z; -- tCAC
        tpd_CASNeg_IO0_pos_edge : VitalDelayType01Z := UnitDelay01Z; -- tCPA
        tpd_OENeg_IO0     : VitalDelayType01Z := UnitDelay01Z;        -- tOEA
        tpd_RASNeg_IO0    : VitalDelayType01Z  := UnitDelay01Z;       -- tRAC
        tpd_A0_IO0        : VitalDelayType01  := UnitDelay01;         -- tAA
        tpd_WENeg_IO0     : VitalDelayType01Z := UnitDelay01Z;        -- tWEZ

        -- tsetup values
        tsetup_A0_RASNeg      : VitalDelayType := UnitDelay; -- tRAL
        tsetup_A0_CASNeg      : VitalDelayType := UnitDelay; -- tCAL
        tsetup_CASNeg_WENeg   : VitalDelayType := UnitDelay; -- tCWD
        tsetup_A0_WENeg       : VitalDelayType := UnitDelay; -- tAWD
        tsetup_IO0_WENeg   : VitalDelayType := UnitDelay; -- tDS
        tsetup_IO0_CASNeg  : VitalDelayType := UnitDelay; -- tDS
        tsetup_RASNeg_CASNeg_read_noedge_posedge  :
                                        VitalDelayType := UnitDelay; -- tCSH
        tsetup_RASNeg_CASNeg_read1_noedge_negedge :
                                        VitalDelayType := UnitDelay; -- tRCD
        tsetup_CASNeg_RASNeg_cas_before2_noedge_negedge :
                                         VitalDelayType := UnitDelay; --tCSR

        -- thold values
        thold_A0_RASNeg    : VitalDelayType := UnitDelay; -- tRAH
        thold_A0_CASNeg    : VitalDelayType := UnitDelay; -- tCAH
        thold_RASNeg_WENeg : VitalDelayType := UnitDelay; -- tRWL
        thold_CASNeg_WENeg : VitalDelayType := UnitDelay; -- tCWL
        thold_WENeg_CASNeg : VitalDelayType := UnitDelay; -- tWCH
        thold_WENeg_RASNeg : VitalDelayType := UnitDelay; -- tWRH
        thold_OENeg_WENeg  : VitalDelayType := UnitDelay; -- tOEH
        thold_CASNeg_OENeg  : VitalDelayType := UnitDelay; --tCOL
        thold_OENeg_CASNeg  : VitalDelayType := UnitDelay; -- tCOP
        thold_IO0_WENeg    : VitalDelayType := UnitDelay; -- tDH
        thold_IO0_CASNeg   : VitalDelayType := UnitDelay; -- tDH
        thold_RASNeg_CASNeg_read_noedge_negedge :
                                           VitalDelayType := UnitDelay; -- tRSH
        thold_CASNeg_RASNeg_cas_before1_noedge_posedge :
                                           VitalDelayType := UnitDelay; --tRPC
        thold_CASNeg_RASNeg_cas_before2_noedge_negedge :
                                           VitalDelayType := UnitDelay; -- tCHR
        thold_RASNeg_CASNeg_cas_before1_noedge_posedge :
                                           VitalDelayType := UnitDelay; -- tCRP
        thold_RASNeg_CASNeg_page_rd_noedge_posedge     :
                                           VitalDelayType := UnitDelay; -- tCPRH
        thold_WENeg_CASNeg_page_rd_noedge_posedge      :
                                           VitalDelayType := UnitDelay; -- tRCHC
        thold_WENeg_CASNeg_page_rd_mod_noedge_posedge  :
                                           VitalDelayType := UnitDelay; -- tCPW

        -- tpw values
        tpw_CASNeg_negedge    : VitalDelayType := UnitDelay; -- tCAS
        tpw_RASNeg_negedge    : VitalDelayType := UnitDelay; -- tRAS
        tpw_CASNeg_posedge    : VitalDelayType := UnitDelay; -- tCP
        tpw_RASNeg_posedge    : VitalDelayType := UnitDelay; -- tRP
        tpw_WENeg_negedge     : VitalDelayType := UnitDelay; -- tWP, tWPE
        tpw_OENeg_posedge     : VitalDelayType := UnitDelay; -- tOEP

        -- tperiod values
        tperiod_CASNeg_page_rd         : VitalDelayType := UnitDelay; -- tHCP
        tperiod_CASNeg_page_rd_mod_wr  : VitalDelayType := UnitDelay; -- tHPRWC
        tperiod_RASNeg                 : VitalDelayType := UnitDelay; -- tRC

        -- tdevice values: values for internal delays
        tdevice_tRASMAX   : VitalDelayType    := 10000 ns; -- TRASMAX
        tdevice_tRASPMAX  : VitalDelayType    := 100000 ns; -- TRASPMAX
        tdevice_tCASMAX   : VitalDelayType    := 10000 ns; -- TCASMAX
        tdevice_tRWC      : VitalDelayType    := 140 ns; -- TRWC
        tdevice_tRAD      : VitalDelayType    := 12 ns; -- TRAD
        tdevice_tRADMAX   : VitalDelayType    := 30 ns; -- TRADMAX
        tdevice_tRCDMAX   : VitalDelayType    := 45 ns; -- TRCDMAX
        tdevice_tRCHR     : VitalDelayType    := 60 ns; -- tRCHR
        tdevice_tRWD      : VitalDelayType    := 79 ns; -- tRWD
        tdevice_tOED      : VitalDelayType    := 15 ns; -- tCDD,tRDD,tWED,tOED

        -- generic control parameters
        InstancePath      : string    := DefaultInstancePath;
        TimingChecksOn    : boolean   := DefaultTimingChecks;
        MsgOn             : boolean   := DefaultMsgOn;
        XOn               : boolean   := DefaultXon;

        -- memory file to be loaded
        mem_file_name     : string    := "none";
        UserPreload       : boolean   := FALSE;

        -- For FMF SDF technology file usage
        TimingModel       : string    := DefaultTimingModel
    );
    PORT (
        CASNeg          : IN    std_ulogic := 'U';
        RASNeg          : IN    std_ulogic := 'U';
        WENeg           : IN    std_ulogic := 'U';
        OENeg           : IN    std_ulogic := 'U';
        A0              : IN    std_ulogic := 'U';
        A1              : IN    std_ulogic := 'U';
        A2              : IN    std_ulogic := 'U';
        A3              : IN    std_ulogic := 'U';
        A4              : IN    std_ulogic := 'U';
        A5              : IN    std_ulogic := 'U';
        A6              : IN    std_ulogic := 'U';
        A7              : IN    std_ulogic := 'U';
        A8              : IN    std_ulogic := 'U';
        A9              : IN    std_ulogic := 'U';
        A10             : IN    std_ulogic := 'U';
        A11             : IN    std_ulogic := 'U';
        IO0             : INOUT std_ulogic := 'U';
        IO1             : INOUT std_ulogic := 'U';
        IO2             : INOUT std_ulogic := 'U';
        IO3             : INOUT std_ulogic := 'U';
        IO4             : INOUT std_ulogic := 'U';
        IO5             : INOUT std_ulogic := 'U';
        IO6             : INOUT std_ulogic := 'U';
        IO7             : INOUT std_ulogic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 OF hm5113805f : ENTITY IS TRUE;
END hm5113805f;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral OF hm5113805f IS
    ATTRIBUTE VITAL_LEVEL0 OF vhdl_behavioral : ARCHITECTURE IS TRUE;

    CONSTANT PartID         : string := "hm5113805f";
    CONSTANT MaxData        : natural := 16#FF#;
    CONSTANT MemSize        : natural := 16#FFFFFF#;
    CONSTANT RowSize        : natural := 16#FFF#;
    CONSTANT ColSize        : natural := 16#FFF#;

    -- ipd
    SIGNAL CASNeg_ipd       : std_ulogic := 'U';
    SIGNAL RASNeg_ipd       : std_ulogic := 'U';
    SIGNAL WENeg_ipd        : std_ulogic := 'U';
    SIGNAL OENeg_ipd        : std_ulogic := 'U';
    SIGNAL A0_ipd           : std_ulogic := 'U';
    SIGNAL A1_ipd           : std_ulogic := 'U';
    SIGNAL A2_ipd           : std_ulogic := 'U';
    SIGNAL A3_ipd           : std_ulogic := 'U';
    SIGNAL A4_ipd           : std_ulogic := 'U';
    SIGNAL A5_ipd           : std_ulogic := 'U';
    SIGNAL A6_ipd           : std_ulogic := 'U';
    SIGNAL A7_ipd           : std_ulogic := 'U';
    SIGNAL A8_ipd           : std_ulogic := 'U';
    SIGNAL A9_ipd           : std_ulogic := 'U';
    SIGNAL A10_ipd          : std_ulogic := 'U';
    SIGNAL A11_ipd          : std_ulogic := 'U';
    SIGNAL IO0_ipd          : std_ulogic := 'U';
    SIGNAL IO1_ipd          : std_ulogic := 'U';
    SIGNAL IO2_ipd          : std_ulogic := 'U';
    SIGNAL IO3_ipd          : std_ulogic := 'U';
    SIGNAL IO4_ipd          : std_ulogic := 'U';
    SIGNAL IO5_ipd          : std_ulogic := 'U';
    SIGNAL IO6_ipd          : std_ulogic := 'U';
    SIGNAL IO7_ipd          : std_ulogic := 'U';

    -- nwv
    SIGNAL CASNeg_nwv       : std_ulogic := 'U';
    SIGNAL RASNeg_nwv       : std_ulogic := 'U';
    SIGNAL WENeg_nwv        : std_ulogic := 'U';
    SIGNAL OENeg_nwv        : std_ulogic := 'U';
    SIGNAL A0_nwv           : std_ulogic := 'U';
    SIGNAL A1_nwv           : std_ulogic := 'U';
    SIGNAL A2_nwv           : std_ulogic := 'U';
    SIGNAL A3_nwv           : std_ulogic := 'U';
    SIGNAL A4_nwv           : std_ulogic := 'U';
    SIGNAL A5_nwv           : std_ulogic := 'U';
    SIGNAL A6_nwv           : std_ulogic := 'U';
    SIGNAL A7_nwv           : std_ulogic := 'U';
    SIGNAL A8_nwv           : std_ulogic := 'U';
    SIGNAL A9_nwv           : std_ulogic := 'U';
    SIGNAL A10_nwv          : std_ulogic := 'U';
    SIGNAL A11_nwv          : std_ulogic := 'U';
    SIGNAL IO0_nwv          : std_ulogic := 'U';
    SIGNAL IO1_nwv          : std_ulogic := 'U';
    SIGNAL IO2_nwv          : std_ulogic := 'U';
    SIGNAL IO3_nwv          : std_ulogic := 'U';
    SIGNAL IO4_nwv          : std_ulogic := 'U';
    SIGNAL IO5_nwv          : std_ulogic := 'U';
    SIGNAL IO6_nwv          : std_ulogic := 'U';
    SIGNAL IO7_nwv          : std_ulogic := 'U';

    ---  internal delays
    SIGNAL tRCHR_tmp_in      : std_ulogic := '0';
    SIGNAL tRCHR_tmp_out     : std_ulogic := '0';
    SIGNAL tRWD_tmp_in       : std_ulogic := '0';
    SIGNAL tRWD_tmp_out      : std_ulogic := '0';
    SIGNAL TRASMAX_tmp_out   : std_ulogic := '0';
    SIGNAL TRASMAX_tmp_in    : std_ulogic := '0';
    SIGNAL TRASPMAX_tmp_out  : std_ulogic := '0';
    SIGNAL TRASPMAX_tmp_in   : std_ulogic := '0';
    SIGNAL TCASMAX_tmp_out   : std_ulogic := '0';
    SIGNAL TCASMAX_tmp_in    : std_ulogic := '0';
    SIGNAL TRWC_tmp_out      : std_ulogic := '0';
    SIGNAL TRWC_tmp_in       : std_ulogic := '0';
    SIGNAL TRAD_tmp_out      : std_ulogic := '0';
    SIGNAL TRAD_tmp_in       : std_ulogic := '0';
    SIGNAL TOED_tmp_out      : std_ulogic := '0';
    SIGNAL TOED_tmp_in       : std_ulogic := '0';
    SIGNAL TRADMAX_tmp_out   : std_ulogic := '0';
    SIGNAL TRADMAX_tmp_in    : std_ulogic := '0';
    SIGNAL TRCDMAX_tmp_out   : std_ulogic := '0';
    SIGNAL TRCDMAX_tmp_in    : std_ulogic := '0';

    SIGNAL TRASMAX_out   : std_ulogic := '0';
    SIGNAL TRASMAX_in    : std_ulogic := '0';
    SIGNAL TRASPMAX_out  : std_ulogic := '0';
    SIGNAL TRASPMAX_in   : std_ulogic := '0';
    SIGNAL TCASMAX_out   : std_ulogic := '0';
    SIGNAL TCASMAX_in    : std_ulogic := '0';
    SIGNAL TRAD_out      : std_ulogic := '0';
    SIGNAL TRAD_in       : std_ulogic := '0';
    SIGNAL TRADMAX_out   : std_ulogic := '0';
    SIGNAL TRADMAX_in    : std_ulogic := '0';
    SIGNAL TRCDMAX_out   : std_ulogic := '0';
    SIGNAL TRCDMAX_in    : std_ulogic := '0';
    SIGNAL tRCHR_in      : std_ulogic := '0';
    SIGNAL tRCHR_out     : std_ulogic := '0';
    SIGNAL tOED_in       : std_ulogic := '0';
    SIGNAL tOED_out      : std_ulogic := '0';
    SIGNAL tRWD_in       : std_ulogic := '0';
    SIGNAL tRWD_out      : std_ulogic := '0';

BEGIN

    ----------------------------------------------------------------------------
    -- Internal Delays
    ----------------------------------------------------------------------------

    TRASMAX  : VitalBuf(tRASMAX_tmp_out, tRASMAX_tmp_in,
                                                 (tdevice_tRASMAX, UnitDelay));
    TRASPMAX : VitalBuf(tRASPMAX_tmp_out, tRASPMAX_tmp_in,
                                                 (tdevice_tRASPMAX, UnitDelay));
    TCASMAX  : VitalBuf(tCASMAX_tmp_out, tCASMAX_tmp_in,
                                                 (tdevice_tCASMAX, UnitDelay));
    TRWC     : VitalBuf(tRWC_tmp_out, tRWC_tmp_in,(tdevice_tRWC, UnitDelay));
    TRAD     : VitalBuf(tRAD_tmp_out, tRAD_tmp_in, (tdevice_tRAD, UnitDelay));
    TRADMAX  : VitalBuf(tRADMAX_tmp_out, tRADMAX_tmp_in,
                                                  (tdevice_tRADMAX, UnitDelay));
    TRCDMAX  : VitalBuf(tRCDMAX_tmp_out, tRCDMAX_tmp_in,
                                                  (tdevice_tRCDMAX, UnitDelay));
    TRCHR  : VitalBuf(tRCHR_tmp_out, tRCHR_tmp_in, (tdevice_tRCHR, UnitDelay));
    TRWD   : VitalBuf(tRWD_tmp_out, tRWD_tmp_in, (tdevice_tRWD, UnitDelay));
    TOED   : VitalBuf(tOED_tmp_out, tOED_tmp_in, (tdevice_tOED, UnitDelay));

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN
        w_01 : VitalWireDelay (CASNeg_ipd, CASNeg, tipd_CASNeg);
        w_02 : VitalWireDelay (RASNeg_ipd, RASNeg, tipd_RASNeg);
        w_03 : VitalWireDelay (WENeg_ipd, WENeg, tipd_WENeg);
        w_04 : VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg);
        w_05 : VitalWireDelay (A0_ipd, A0, tipd_A0);
        w_06 : VitalWireDelay (A1_ipd, A1, tipd_A1);
        w_07 : VitalWireDelay (A2_ipd, A2, tipd_A2);
        w_08 : VitalWireDelay (A3_ipd, A3, tipd_A3);
        w_09 : VitalWireDelay (A4_ipd, A4, tipd_A4);
        w_10 : VitalWireDelay (A5_ipd, A5, tipd_A5);
        w_11 : VitalWireDelay (A6_ipd, A6, tipd_A6);
        w_12 : VitalWireDelay (A7_ipd, A7, tipd_A7);
        w_13 : VitalWireDelay (A8_ipd, A8, tipd_A8);
        w_14 : VitalWireDelay (A9_ipd, A9, tipd_A9);
        w_15 : VitalWireDelay (A10_ipd, A10, tipd_A10);
        w_16 : VitalWireDelay (A11_ipd, A11, tipd_A11);
        w_17 : VitalWireDelay (IO0_ipd, IO0, tipd_IO0);
        w_18 : VitalWireDelay (IO1_ipd, IO1, tipd_IO1);
        w_19 : VitalWireDelay (IO2_ipd, IO2, tipd_IO2);
        w_20 : VitalWireDelay (IO3_ipd, IO3, tipd_IO3);
        w_21 : VitalWireDelay (IO4_ipd, IO4, tipd_IO4);
        w_22 : VitalWireDelay (IO5_ipd, IO5, tipd_IO5);