mt46v16m16.vhd

vhdl cod for ram.For sp3e

            VARIABLE UDQSDrive6 : std_logic;
            VARIABLE UDQSDrive7 : std_logic;
            VARIABLE UDQS_zd   : std_logic;
            VARIABLE UDQS_GlitchData : VitalGlitchDataType;

            VARIABLE UInputReg  : INTEGER RANGE  -2 TO 255;
            VARIABLE LInputReg  : INTEGER RANGE  -2 TO 255;

        PROCEDURE FixColumnAddress( bank : IN NATURAL RANGE 0 TO 3) IS
        BEGIN
           MemAddr(bank)(HiColBit downto 0) := (others => '0');
           MemAddr(bank)(HiColBit downto Burst_Bits) :=
                      AddressIn(HiColBit downto Burst_Bits); --

           Burst_Inc(bank) := to_nat(AddressIn(Burst_Bits-1 downto 0));
           StartAddr(bank) := Burst_Inc(bank) mod 8;
           BaseLoc(bank) := to_nat(MemAddr(bank));
           Location := BaseLoc(bank) + Burst_Inc(bank);
        END PROCEDURE ;

        PROCEDURE ReadFromMem( bank : IN NATURAL RANGE 0 TO 3) IS
        BEGIN
            LDQSDrive:='0';
            UDQSDrive:='0';

            IF LMemData(Bank)(Location) = -2 THEN
                DataDrive(7 downto 0) := (others => 'U');
            ELSIF LMemData(Bank)(Location) = -1 THEN
                DataDrive(7 downto 0) := (others => 'X');
            ELSE
                DataDrive(7 downto 0):=
                    to_slv(LMemData(Bank)(Location),8);
            END IF;

            IF UMemData(Bank)(Location) = -2 THEN
                DataDrive(15 downto 8) := (others => 'U');
            ELSIF UMemData(Bank)(Location) = -1 THEN
                DataDrive(15 downto 8) := (others => 'X');
            ELSE
                DataDrive(15 downto 8) :=
                    to_slv(UMemData(Bank)(Location),8);
            END IF;
        END;

        PROCEDURE WriteToMem( bank : IN NATURAL RANGE 0 TO 3) IS
        BEGIN
            IF LDQS_event_reg THEN
                IF Violation = '0' THEN
                    LMemData(Bank)(Location) := LInputReg;
                ELSE
                    LMemData(Bank)(Location) := -1;
                END IF;
            END IF;
            IF UDQS_event_reg THEN
                IF Violation = '0' THEN
                    UMemData(Bank)(Location) := UInputReg;
                ELSE
                    UMemData(Bank)(Location) := -1;
                END IF;
            END IF;
        END;

        PROCEDURE BurstCtrl( bank : IN NATURAL RANGE 0 TO 3) IS
        BEGIN
            IF (Burst = sequential) THEN
                Burst_Inc(bank) := (Burst_Inc(bank) + 1) MOD
                                    Burst_Length;
            ELSE
                Burst_Inc(bank) := intab(StartAddr(bank))
                                        (Burst_Cnt(bank));
            END IF;
        END;


        BEGIN

            --------------------------------------------------------------------
            -- Timing Check Section
            --------------------------------------------------------------------
            IF (TimingChecksOn) THEN

                VitalSetupHoldCheck (
                    TestSignal      => BAIn,
                    TestSignalName  => "BA",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_DQ0_CLK,
                    SetupLow        => tsetup_DQ0_CLK,
                    HoldHigh        => thold_DQ0_CLK,
                    HoldLow         => thold_DQ0_CLK,
                    CheckEnabled    => chip_en,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_BA_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_BA_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => LDMIn,
                    TestSignalName  => "LDM",
                    RefSignal       => LDQSIn,
                    RefSignalName   => "LDQS",
                    SetupHigh       => tsetup_LDM_LDQS,
                    SetupLow        => tsetup_LDM_LDQS,
                    HoldHigh        => thold_LDM_LDQS,
                    HoldLow         => thold_LDM_LDQS,
                    CheckEnabled    => chip_en,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_LDM_LDQS,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_LDM_LDQS );

                VitalSetupHoldCheck (
                    TestSignal      => UDMIn,
                    TestSignalName  => "UDM",
                    RefSignal       => UDQSIn,
                    RefSignalName   => "UDQS",
                    SetupHigh       => tsetup_LDM_LDQS,
                    SetupLow        => tsetup_LDM_LDQS,
                    HoldHigh        => thold_LDM_LDQS,
                    HoldLow         => thold_LDM_LDQS,
                    CheckEnabled    => chip_en,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_UDM_UDQS,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_UDM_UDQS );

                VitalSetupHoldCheck (
                    TestSignal      => DataIn,
                    TestSignalName  => "Data",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_DQ0_CLK,
                    SetupLow        => tsetup_DQ0_CLK,
                    HoldHigh        => thold_DQ0_CLK,
                    HoldLow         => thold_DQ0_CLK,
                    CheckEnabled    => chip_en AND
                                        NOT(DataIn(0)='X' AND D_zd(0)='Z'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_D0_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_D0_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => DataIn(15 downto 8),
                    TestSignalName  => "Data",
                    RefSignal       => UDQSIn,
                    RefSignalName   => "UDQS",
                    SetupHigh       => tsetup_DQ0_LDQS,
                    SetupLow        => tsetup_DQ0_LDQS,
                    HoldHigh        => thold_DQ0_LDQS,
                    HoldLow         => thold_DQ0_LDQS,
                    CheckEnabled    => chip_en,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_D8_UDQS,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_D8_UDQS );

                VitalSetupHoldCheck (
                    TestSignal      => DataIn(7 downto 0),
                    TestSignalName  => "Data",
                    RefSignal       => LDQSIn,
                    RefSignalName   => "LDQS",
                    SetupHigh       => tsetup_DQ0_LDQS,
                    SetupLow        => tsetup_DQ0_LDQS,
                    HoldHigh        => thold_DQ0_LDQS,
                    HoldLow         => thold_DQ0_LDQS,
                    CheckEnabled    => chip_en,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_D0_LDQS,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_D0_LDQS );

                VitalSetupHoldCheck (
                    TestSignal      => LDQSIn,
                    TestSignalName  => "LDQS",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_LDQS_CLK,
                    HoldHigh        => thold_LDQS_CLK,
                    CheckEnabled    => chip_en AND (NOT LDQSIn=LDQS_zd),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_LDQS_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_LDQS_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => UDQSIn,
                    TestSignalName  => "UDQS",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_LDQS_CLK,
                    HoldHigh        => thold_LDQS_CLK,
                    CheckEnabled    => chip_en AND (NOT UDQSIn=UDQS_zd),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_UDQS_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_UDQS_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => CKEIn,
                    TestSignalName  => "CKE",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_DQ0_CLK,
                    SetupLow        => tsetup_DQ0_CLK,
                    HoldHigh        => thold_DQ0_CLK,
                    HoldLow         => thold_DQ0_CLK,
                    CheckEnabled    => true,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_CKE_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_CKE_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => AddressIn,
                    TestSignalName  => "Address",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_A0_CLK,
                    SetupLow        => tsetup_A0_CLK,
                    HoldHigh        => thold_A0_CLK,
                    HoldLow         => thold_A0_CLK,
                    CheckEnabled    => chip_en,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_Address_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_Address_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => WENegIn,
                    TestSignalName  => "WENeg",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_A0_CLK,
                    SetupLow        => tsetup_A0_CLK,
                    HoldHigh        => thold_A0_CLK,
                    HoldLow         => thold_A0_CLK,
                    CheckEnabled    => chip_en,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_WENeg_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_WENeg_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => RASNegIn,
                    TestSignalName  => "RASNeg",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_A0_CLK,
                    SetupLow        => tsetup_A0_CLK,
                    HoldHigh        => thold_A0_CLK,
                    HoldLow         => thold_A0_CLK,
                    CheckEnabled    => chip_en,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_RASNeg_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_RASNeg_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => CSNegIn,
                    TestSignalName  => "CSNeg",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_A0_CLK,
                    SetupLow        => tsetup_A0_CLK,
                    HoldHigh        => thold_A0_CLK,
                    HoldLow         => thold_A0_CLK,
                    CheckEnabled    => chip_en,
                    RefTransition   => '/',