mt46v16m16.vhd

vhdl cod for ram.For sp3e

    CLKIn       <= clk_tmp2;    --fixed
    CLKNegIn    <= clkneg_tmp2; --fixed
    ---------------------------------------------------------------------------

    PoweredUp <= true after tpowerup;
    CLKcomb <= CLKIn AND not(CLKNegIn);

    ----------------------------------------------
    -- DLL model functional section            ---
    ----------------------------------------------
    DLL: PROCESS(CLKcomb, CLKIn, CLKNegIn, CKSKWtrg)

        -- Timing Check Variables
        VARIABLE Sviol_CLK_CLKNeg    : X01 := '0';
        VARIABLE SD_CLK_CLKNeg       : VitalSkewDataType := VitalSkewDataInit;

        -- Functionality Results Variables
        VARIABLE Violation  : X01 := '0';

        VARIABLE Previous     : Time := 0 ns;
        VARIABLE TmpPer       : Time := 0 ns;

    BEGIN

        --------------------------------------------------------------------
        -- Timing Check Section
        --------------------------------------------------------------------
        IF (TimingChecksOn) THEN

            VitalOutPhaseSkewCheck (
                Signal1         => CLKIn,
                Signal1Name     =>  "CLK",
                Signal2         => CLKNegIn,
                Signal2Name     =>  "CLKNeg",
                SkewS1S2RiseFall => tskew_CLK_CLKNeg,
                SkewS2S1RiseFall => tskew_CLK_CLKNeg,
                SkewS1S2FallRise => tskew_CLK_CLKNeg,
                SkewS2S1FallRise => tskew_CLK_CLKNeg,
                CheckEnabled    => TRUE,
                HeaderMsg       => InstancePath & PartID,
                SkewData        => SD_CLK_CLKNeg,
                Trigger         => CKSKWtrg,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Sviol_CLK_CLKNeg );

            Violation := Sviol_CLK_CLKNeg;

        END IF; -- Timing Check Section

    --------------------------------------------------------------------
    -- Functional Section
    --------------------------------------------------------------------

        IF rising_edge(CLKcomb) AND  DLL_reset = TRUE THEN
            TmpPer := NOW - Previous;
            IF TmpPer > 0 ns THEN
                PERIOD <= TmpPer;
            END IF;
            Previous := NOW;
            HalfPer <= PERIOD/2;
            dlldelay <= PERIOD - tpd_CLK_DQ1;
        END IF;
    END PROCESS DLL;

    CLK_temp : PROCESS (CLKcomb)-- generating internal clock from DLL

    BEGIN
        IF DLL_reset = FALSE THEN
          CLKtemp <= TRANSPORT not(CLKtemp) AFTER HalfPer;
        END IF;
    END PROCESS;

    CLK_int : PROCESS (CLKcomb, CLKtemp)-- Passing clock based on DLL_EN

    BEGIN
        IF DLL_EN AND NOT DLL_RESET then
            CLKint <= TRANSPORT CLKtemp AFTER dlldelay;
            CLKint <= CLKcomb;
        END IF;
    END PROCESS;

    Detect_tWR_Violation : PROCESS( wrt_glitch, Viol_tWR_out )
    BEGIN
        IF rising_edge(wrt_glitch) THEN
            Viol_tWR_in(wrt_bank) <= '0', '1' AFTER 1 ns;
        END IF;
        IF rising_edge(Viol_tWR_out(0)) THEN
            Viol_tWR_in(0) <= '0';
        END IF;
        IF rising_edge(Viol_tWR_out(1)) THEN
            Viol_tWR_in(1) <= '0';
        END IF;
        IF rising_edge(Viol_tWR_out(2)) THEN
            Viol_tWR_in(2) <= '0';
        END IF;
        IF rising_edge(Viol_tWR_out(3)) THEN
            Viol_tWR_in(3) <= '0';
        END IF;
    END PROCESS Detect_tWR_Violation;

    tWR_Timing_Control : PROCESS( Viol_tWR_in )
    BEGIN
        IF rising_edge(Viol_tWR_in(0)) THEN
            Viol_tWR_out(0) <= '0', '1' AFTER (tdevice_TWR - 1 ns);
        END IF;
        IF rising_edge(Viol_tWR_in(1)) THEN
            Viol_tWR_out(1) <= '0', '1' AFTER (tdevice_TWR - 1 ns);
        END IF;
        IF rising_edge(Viol_tWR_in(2)) THEN
            Viol_tWR_out(2) <= '0', '1' AFTER (tdevice_TWR - 1 ns);
        END IF;
        IF rising_edge(Viol_tWR_in(3)) THEN
            Viol_tWR_out(3) <= '0', '1' AFTER (tdevice_TWR - 1 ns);
        END IF;
    END PROCESS tWR_Timing_Control;


    ----------------------------------------------------------------------------
    -- Main Behavior Process
    ----------------------------------------------------------------------------
        Behavior : PROCESS (BAIn, LDMIn, UDMIn, LDQSIn, UDQSIn, DataIn, CLKIn,
                            CLKNegIn, CLKint, CKEIn, AddressIn, WENegIn,
                            RASNegIn, CSNegIn, CASNegIn, PoweredUp)


            -- Type definition for commands
            TYPE command_type is (desl,
                                  nop,
                                  bst,
                                  read,
                                  writ,
                                  act,
                                  pre,
                                  mrs,
                                  ref
                                 );

            -- Timing Check Variables
            VARIABLE Tviol_BA_CLK       : X01 := '0';
            VARIABLE TD_BA_CLK          : VitalTimingDataType;

            VARIABLE Tviol_LDM_LDQS     : X01 := '0';
            VARIABLE TD_LDM_LDQS        : VitalTimingDataType;

            VARIABLE Tviol_UDM_UDQS     : X01 := '0';
            VARIABLE TD_UDM_UDQS        : VitalTimingDataType;

            VARIABLE Tviol_D0_CLK       : X01 := '0';
            VARIABLE TD_D0_CLK          : VitalTimingDataType;

            VARIABLE Tviol_LDQS_CLK     : X01 := '0';
            VARIABLE TD_LDQS_CLK        : VitalTimingDataType;

            VARIABLE Tviol_UDQS_CLK     : X01 := '0';
            VARIABLE TD_UDQS_CLK        : VitalTimingDataType;

            VARIABLE Tviol_CKE_CLK      : X01 := '0';
            VARIABLE TD_CKE_CLK         : VitalTimingDataType;

            VARIABLE Tviol_Address_CLK  : X01 := '0';
            VARIABLE TD_Address_CLK     : VitalTimingDataType;

            VARIABLE Tviol_WENeg_CLK    : X01 := '0';
            VARIABLE TD_WENeg_CLK       : VitalTimingDataType;

            VARIABLE Tviol_RASNeg_CLK   : X01 := '0';
            VARIABLE TD_RASNeg_CLK      : VitalTimingDataType;

            VARIABLE Tviol_CSNeg_CLK    : X01 := '0';
            VARIABLE TD_CSNeg_CLK       : VitalTimingDataType;

            VARIABLE Tviol_CASNeg_CLK   : X01 := '0';
            VARIABLE TD_CASNeg_CLK      : VitalTimingDataType;

            VARIABLE Tviol_D8_UDQS      : X01 := '0';
            VARIABLE TD_D8_UDQS         : VitalTimingDataType;

            VARIABLE Tviol_D0_LDQS      : X01 := '0';
            VARIABLE TD_D0_LDQS         : VitalTimingDataType;

            VARIABLE Pviol_CLK     : X01 := '0';
            VARIABLE PD_CLK        : VitalPeriodDataType := VitalPeriodDataInit;

            VARIABLE Pviol_UDQS    : X01 := '0';
            VARIABLE PD_UDQS       : VitalPeriodDataType := VitalPeriodDataInit;

            VARIABLE Pviol_LDQS    : X01 := '0';
            VARIABLE PD_LDQS       : VitalPeriodDataType := VitalPeriodDataInit;

            -- Memory array declaration
            TYPE MemStore IS ARRAY (0 to depth) OF INTEGER
                             RANGE  -2 TO 255;

            TYPE MemBlock IS ARRAY (0 to 3) OF MemStore;
            TYPE mode_set_type IS (standard, extended);
            TYPE Burst_type IS (sequential, interleave);
            TYPE Write_Burst_type IS (programmed, single);
            TYPE sequence IS ARRAY (0 to 7) OF NATURAL RANGE 0 to 7;
            TYPE seqtab IS ARRAY (0 to 7) OF sequence;
            TYPE MemLoc IS ARRAY (0 to 3) OF
                 std_logic_vector(HiAddrBit+HiColBit+1 DOWNTO 0);
            TYPE burst_counter IS ARRAY (0 to 3) OF NATURAL RANGE 0 to 257;
            TYPE StartAddr_type IS ARRAY (0 to 3) OF NATURAL RANGE 0 TO 7;
            TYPE Burst_Inc_type IS ARRAY (0 to 3) OF NATURAL RANGE 0 TO 8;
            TYPE BaseLoc_type IS ARRAY (0 to 3) OF NATURAL RANGE 0 TO depth;
            SUBTYPE OutWord IS std_logic_vector(15 DOWNTO 0);

            CONSTANT seq0 : sequence := (0 & 1 & 2 & 3 & 4 & 5 & 6 & 7);
            CONSTANT seq1 : sequence := (1 & 0 & 3 & 2 & 5 & 4 & 7 & 6);
            CONSTANT seq2 : sequence := (2 & 3 & 0 & 1 & 6 & 7 & 4 & 5);
            CONSTANT seq3 : sequence := (3 & 2 & 1 & 0 & 7 & 6 & 5 & 4);
            CONSTANT seq4 : sequence := (4 & 5 & 6 & 7 & 0 & 1 & 2 & 3);
            CONSTANT seq5 : sequence := (5 & 4 & 7 & 6 & 1 & 0 & 3 & 2);
            CONSTANT seq6 : sequence := (6 & 7 & 4 & 5 & 2 & 3 & 0 & 1);
            CONSTANT seq7 : sequence := (7 & 6 & 5 & 4 & 3 & 2 & 1 & 0);
            CONSTANT intab : seqtab := (seq0, seq1, seq2, seq3, seq4, seq5,
                                        seq6, seq7);

            FILE mem_file       : text IS mem_file_name;
            VARIABLE UMemData   : MemBlock;
            VARIABLE LMemData   : MemBlock;
            VARIABLE file_bank  : NATURAL := 0;
            VARIABLE ind        : NATURAL := 0;
            VARIABLE buf        : line;
            VARIABLE mode_set_ind : mode_set_type ;

            VARIABLE MemAddr      : MemLoc;
            VARIABLE Location     : NATURAL RANGE 0 TO depth := 0;
            VARIABLE Location2    : NATURAL RANGE 0 TO depth := 0;
            VARIABLE BaseLoc      : BaseLoc_type;
            VARIABLE Burst_Inc    : Burst_Inc_type;
            VARIABLE StartAddr    : StartAddr_type;

            VARIABLE Burst_Length : NATURAL RANGE 2 TO 8 := 2;
            VARIABLE Burst_Bits   : NATURAL RANGE 1 TO 3 := 1;
            VARIABLE Burst        : Burst_Type;
            VARIABLE Burst_Cnt    : burst_counter;

            VARIABLE command    : command_type;
            VARIABLE written    : boolean := false;
            VARIABLE chip_en    : boolean := false;
            VARIABLE write_to_write : boolean := false;
            VARIABLE LDQS_event_reg : boolean := false;
            VARIABLE UDQS_event_reg : boolean := false;

            VARIABLE ModeReg    : std_logic_vector(12 DOWNTO 0)
                                   := (OTHERS => 'X');
            VARIABLE ExtModeReg    : std_logic_vector(12 DOWNTO 0)
                                   := (OTHERS => 'X');

            VARIABLE Ref_Cnt      : NATURAL RANGE 0 TO 8192 := 0;
            VARIABLE next_ref     : TIME;
            VARIABLE BankString   : STRING(8 DOWNTO 1) := " Bank-X ";

            -- Functionality Results Variables
            VARIABLE Violation  : X01 := '0';
            VARIABLE DataDriveOut :  std_logic_vector(HiDataBit DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE DataDrive  : OutWord;
            VARIABLE DataDrive1 : OutWord;
            VARIABLE DataDrive2 : OutWord;
            VARIABLE DataDrive3 : OutWord;
            VARIABLE DataDrive4 : OutWord;
            VARIABLE DataDrive5 : OutWord;
            VARIABLE DataDrive6 : OutWord;
            VARIABLE LDM_reg0  : UX01;
            VARIABLE LDM_reg1  : UX01;
            VARIABLE LDM_reg2  : UX01;

            VARIABLE UDM_reg0  : UX01;
            VARIABLE UDM_reg1  : UX01;
            VARIABLE UDM_reg2  : UX01;

            VARIABLE LDQSDriveOut : std_logic;
            VARIABLE LDQSDrive  : std_logic;
            VARIABLE LDQSDrive1 : std_logic;
            VARIABLE LDQSDrive2 : std_logic;
            VARIABLE LDQSDrive3 : std_logic;
            VARIABLE LDQSDrive4 : std_logic;
            VARIABLE LDQSDrive5 : std_logic;
            VARIABLE LDQSDrive6 : std_logic;
            VARIABLE LDQSDrive7 : std_logic;
            VARIABLE LDQS_zd   : std_logic;
            VARIABLE LDQS_GlitchData : VitalGlitchDataType;

            VARIABLE UDQSDriveOut : std_logic;
            VARIABLE UDQSDrive  : std_logic;
            VARIABLE UDQSDrive1 : std_logic;
            VARIABLE UDQSDrive2 : std_logic;
            VARIABLE UDQSDrive3 : std_logic;
            VARIABLE UDQSDrive4 : std_logic;
            VARIABLE UDQSDrive5 : std_logic;