mt46v16m16.vhd

vhdl cod for ram.For sp3e

    SIGNAL A9_nwv              : UX01 := 'U';
    SIGNAL A10_nwv             : UX01 := 'U';
    SIGNAL A11_nwv             : UX01 := 'U';
    SIGNAL A12_nwv             : UX01 := 'U';
    SIGNAL CLK_nwv             : std_ulogic := 'U';
    SIGNAL CLKNeg_nwv          : std_ulogic := 'U';
    SIGNAL CKE_nwv             : std_ulogic := 'U';
    SIGNAL WENeg_nwv           : std_ulogic := 'U';
    SIGNAL RASNeg_nwv          : std_ulogic := 'U';
    SIGNAL CSNeg_nwv           : std_ulogic := 'U';
    SIGNAL CASNeg_nwv          : std_ulogic := 'U';

    SIGNAL CKSKWtrg          : std_ulogic := '0';
    SIGNAL rct_in            : std_ulogic := '0';
    SIGNAL rct_out           : std_ulogic := '0';
    SIGNAL rcdt_in           : std_ulogic_vector(3 downto 0) := (others => '0');
    SIGNAL rcdt_out          : std_ulogic_vector(3 downto 0) := (others => '0');
    SIGNAL pre_in            : std_ulogic := '0';
    SIGNAL pre_out           : std_ulogic := '0';
    SIGNAL refreshed_in      : std_ulogic := '0';
    SIGNAL refreshed_out     : std_ulogic := '0';
    SIGNAL rfc_out           : std_ulogic := '0';
    SIGNAL rfc_in            : std_ulogic := '0';
    SIGNAL wrt_in            : std_ulogic := '0';
    SIGNAL wrt_out           : std_ulogic := '0';
    SIGNAL ras_in            : std_ulogic_vector(3 downto 0) := (others => '0');
    SIGNAL ras_out           : std_ulogic_vector(3 downto 0) := (others => '0');
    SIGNAL wrt_glitch        : std_ulogic := '0';
    SIGNAL Viol_tWR_in       : std_ulogic_vector(3 downto 0) := (others => '0');
    SIGNAL Viol_tWR_out      : std_ulogic_vector(3 downto 0) := (others => '1');

    SHARED VARIABLE cur_bank : natural range 0 to hi_bank;
    SHARED VARIABLE wrt_bank : natural range 0 to hi_bank;


BEGIN

    ----------------------------------------------------------------------------
    -- Internal Delays
    ----------------------------------------------------------------------------
    -- Artificial VITAL primitives to incorporate internal delays
    REF : VitalBuf (refreshed_out, refreshed_in, (UnitDelay, tdevice_REF));
    TRC : VitalBuf (rct_out, rct_in, (tdevice_TRC, VitalZeroDelay));
    TRCD : VitalBuf (rcdt_out(0), rcdt_in(0), (VitalZeroDelay, tdevice_TRCD));
    TRCD1 : VitalBuf (rcdt_out(1), rcdt_in(1), (VitalZeroDelay, tdevice_TRCD));
    TRCD2 : VitalBuf (rcdt_out(2), rcdt_in(2), (VitalZeroDelay, tdevice_TRCD));
    TRCD3 : VitalBuf (rcdt_out(3), rcdt_in(3), (VitalZeroDelay, tdevice_TRCD));
    TRP : VitalBuf (pre_out, pre_in, (tdevice_TRP, UnitDelay));
    TRFC : VitalBuf (rfc_out, rfc_in, (tdevice_TRFC, UnitDelay));
    TWR : VitalBuf (wrt_out, wrt_in, (UnitDelay, tdevice_TWR));
    TRAS : VitalBuf (ras_out(0), ras_in(0), tdevice_TRAS);
    TRAS1 : VitalBuf (ras_out(1), ras_in(1), tdevice_TRAS);
    TRAS2 : VitalBuf (ras_out(2), ras_in(2), tdevice_TRAS);
    TRAS3 : VitalBuf (ras_out(3), ras_in(3), tdevice_TRAS);

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1 : VitalWireDelay (BA0_ipd, BA0, tipd_BA0);
        w_2 : VitalWireDelay (BA1_ipd, BA1, tipd_BA1);
        w_3 : VitalWireDelay (LDQS_ipd, LDQS, tipd_LDQS);
        w_51: VitalWireDelay (UDQS_ipd, UDQS, tipd_UDQS);
        w_4 : VitalWireDelay (LDM_ipd, LDM, tipd_LDM);
        w_52: VitalWireDelay (UDM_ipd, UDM, tipd_UDM);
        w_5 : VitalWireDelay (DQ0_ipd, DQ0, tipd_DQ0);
        w_6 : VitalWireDelay (DQ1_ipd, DQ1, tipd_DQ1);
        w_7 : VitalWireDelay (DQ2_ipd, DQ2, tipd_DQ2);
        w_8 : VitalWireDelay (DQ3_ipd, DQ3, tipd_DQ3);
        w_9 : VitalWireDelay (DQ4_ipd, DQ4, tipd_DQ4);
        w_10 : VitalWireDelay (DQ5_ipd, DQ5, tipd_DQ5);
        w_11 : VitalWireDelay (DQ6_ipd, DQ6, tipd_DQ6);
        w_12 : VitalWireDelay (DQ7_ipd, DQ7, tipd_DQ7);
        w_55 : VitalWireDelay (DQ8_ipd, DQ8, tipd_DQ8);
        w_56 : VitalWireDelay (DQ9_ipd, DQ9, tipd_DQ9);
        w_57 : VitalWireDelay (DQ10_ipd, DQ10, tipd_DQ10);
        w_58 : VitalWireDelay (DQ11_ipd, DQ11, tipd_DQ11);
        w_59 : VitalWireDelay (DQ12_ipd, DQ12, tipd_DQ12);
        w_60 : VitalWireDelay (DQ13_ipd, DQ13, tipd_DQ13);
        w_61 : VitalWireDelay (DQ14_ipd, DQ14, tipd_DQ14);
        w_62 : VitalWireDelay (DQ15_ipd, DQ15, tipd_DQ15);
        w_21 : VitalWireDelay (CLKNeg_ipd, CLKNeg, tipd_CLKNeg);
        w_22 : VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
        w_23 : VitalWireDelay (CKE_ipd, CKE, tipd_CKE);
        w_24 : VitalWireDelay (A0_ipd, A0, tipd_A0);
        w_25 : VitalWireDelay (A1_ipd, A1, tipd_A1);
        w_26 : VitalWireDelay (A2_ipd, A2, tipd_A2);
        w_27 : VitalWireDelay (A3_ipd, A3, tipd_A3);
        w_28 : VitalWireDelay (A4_ipd, A4, tipd_A4);
        w_29 : VitalWireDelay (A5_ipd, A5, tipd_A5);
        w_30 : VitalWireDelay (A6_ipd, A6, tipd_A6);
        w_31 : VitalWireDelay (A7_ipd, A7, tipd_A7);
        w_32 : VitalWireDelay (A8_ipd, A8, tipd_A8);
        w_33 : VitalWireDelay (A9_ipd, A9, tipd_A9);
        w_34 : VitalWireDelay (A10_ipd, A10, tipd_A10);
        w_35 : VitalWireDelay (A11_ipd, A11, tipd_A11);
        w_36 : VitalWireDelay (A12_ipd, A12, tipd_A12);
        w_47 : VitalWireDelay (WENeg_ipd, WENeg, tipd_WENeg);
        w_48 : VitalWireDelay (RASNeg_ipd, RASNeg, tipd_RASNeg);
        w_49 : VitalWireDelay (CSNeg_ipd, CSNeg, tipd_CSNeg);
        w_50 : VitalWireDelay (CASNeg_ipd, CASNeg, tipd_CASNeg);

    END BLOCK;

    WENeg_nwv <= To_UX01(WENeg_ipd);
    RASNeg_nwv <= To_UX01(RASNeg_ipd);
    CSNeg_nwv <= To_UX01(CSNeg_ipd);
    CASNeg_nwv <= To_UX01(CASNeg_ipd);
    CLKNeg_nwv <= To_UX01(CLKNeg_ipd);
    CLK_nwv <= To_UX01(CLK_ipd);
    CKE_nwv <= To_UX01(CKE_ipd);
    BA0_nwv <= To_UX01(BA0_ipd);
    BA1_nwv <= To_UX01(BA1_ipd);
    LDM_nwv <= To_UX01(LDM_ipd);
    UDM_nwv <= To_UX01(UDM_ipd);
    LDQS_nwv <= To_UX01(LDQS_ipd);
    UDQS_nwv <= To_UX01(UDQS_ipd);
    DQ0_nwv <= To_UX01(DQ0_ipd);
    DQ1_nwv <= To_UX01(DQ1_ipd);
    DQ2_nwv <= To_UX01(DQ2_ipd);
    DQ3_nwv <= To_UX01(DQ3_ipd);
    DQ4_nwv <= To_UX01(DQ4_ipd);
    DQ5_nwv <= To_UX01(DQ5_ipd);
    DQ6_nwv <= To_UX01(DQ6_ipd);
    DQ7_nwv <= To_UX01(DQ7_ipd);
    DQ8_nwv <= To_UX01(DQ8_ipd);
    DQ9_nwv <= To_UX01(DQ9_ipd);
    DQ10_nwv <= To_UX01(DQ10_ipd);
    DQ11_nwv <= To_UX01(DQ11_ipd);
    DQ12_nwv <= To_UX01(DQ12_ipd);
    DQ13_nwv <= To_UX01(DQ13_ipd);
    DQ14_nwv <= To_UX01(DQ14_ipd);
    DQ15_nwv <= To_UX01(DQ15_ipd);
    A0_nwv <= To_UX01(A0_ipd);
    A1_nwv <= To_UX01(A1_ipd);
    A2_nwv <= To_UX01(A2_ipd);
    A3_nwv <= To_UX01(A3_ipd);
    A4_nwv <= To_UX01(A4_ipd);
    A5_nwv <= To_UX01(A5_ipd);
    A6_nwv <= To_UX01(A6_ipd);
    A7_nwv <= To_UX01(A7_ipd);
    A8_nwv <= To_UX01(A8_ipd);
    A9_nwv <= To_UX01(A9_ipd);
    A10_nwv <= To_UX01(A10_ipd);
    A11_nwv <= To_UX01(A11_ipd);
    A12_nwv <= To_UX01(A12_ipd);

    ----------------------------------------------------------------------------
    -- Main Behavior Block
    ----------------------------------------------------------------------------
    Main : BLOCK

        PORT (
            BAIn            : IN    std_logic_vector(1 downto 0);
            LDMIn           : IN    std_ulogic := 'U';
            UDMIn           : IN    std_ulogic := 'U';
            LDQSIn          : IN    std_ulogic := 'U';
            UDQSIn          : IN    std_ulogic := 'U';
            DataIn          : IN    std_logic_vector(HiDataBit downto 0);
            DataOut         : OUT   std_logic_vector(HiDataBit downto 0)
                                                     := (others => 'Z');
            LDQSOut         : OUT   std_ulogic := 'Z';
            UDQSOut         : OUT   std_ulogic := 'Z';
            CLK_In          : IN    std_ulogic := 'U';
            CLKNeg_In       : IN    std_ulogic := 'U';
            CKEIn           : IN    std_ulogic := 'U';
            AddressIn       : IN    std_logic_vector(HiAddrBit downto 0);
            WENegIn         : IN    std_ulogic := 'U';
            RASNegIn        : IN    std_ulogic := 'U';
            CSNegIn         : IN    std_ulogic := 'U';
            CASNegIn        : IN    std_ulogic := 'U'
        );
        PORT MAP (
            BAIn(0) => BA0_nwv,
            BAIn(1) => BA1_nwv,
            LDMIn => LDM_nwv,
            UDMIn => UDM_nwv,
            LDQSIn => LDQS_nwv,
            LDQSOut => LDQS,
            UDQSIn => UDQS_nwv,
            UDQSOut => UDQS,
            DataOut(0) =>  DQ0,
            DataOut(1) =>  DQ1,
            DataOut(2) =>  DQ2,
            DataOut(3) =>  DQ3,
            DataOut(4) =>  DQ4,
            DataOut(5) =>  DQ5,
            DataOut(6) =>  DQ6,
            DataOut(7) =>  DQ7,
            DataOut(8) =>  DQ8,
            DataOut(9) =>  DQ9,
            DataOut(10) =>  DQ10,
            DataOut(11) =>  DQ11,
            DataOut(12) =>  DQ12,
            DataOut(13) =>  DQ13,
            DataOut(14) =>  DQ14,
            DataOut(15) =>  DQ15,
            DataIn(0) =>  DQ0_nwv,
            DataIn(1) =>  DQ1_nwv,
            DataIn(2) =>  DQ2_nwv,
            DataIn(3) =>  DQ3_nwv,
            DataIn(4) =>  DQ4_nwv,
            DataIn(5) =>  DQ5_nwv,
            DataIn(6) =>  DQ6_nwv,
            DataIn(7) =>  DQ7_nwv,
            DataIn(8) =>  DQ8_nwv,
            DataIn(9) =>  DQ9_nwv,
            DataIn(10) =>  DQ10_nwv,
            DataIn(11) =>  DQ11_nwv,
            DataIn(12) =>  DQ12_nwv,
            DataIn(13) =>  DQ13_nwv,
            DataIn(14) =>  DQ14_nwv,
            DataIn(15) =>  DQ15_nwv,
            CLK_In => CLK_nwv,
            CLKNEG_In => CLKNeg_nwv,
            CKEIn => CKE_nwv,
            AddressIn(0) => A0_nwv,
            AddressIn(1) => A1_nwv,
            AddressIn(2) => A2_nwv,
            AddressIn(3) => A3_nwv,
            AddressIn(4) => A4_nwv,
            AddressIn(5) => A5_nwv,
            AddressIn(6) => A6_nwv,
            AddressIn(7) => A7_nwv,
            AddressIn(8) => A8_nwv,
            AddressIn(9) => A9_nwv,
            AddressIn(10) => A10_nwv,
            AddressIn(11) => A11_nwv,
            AddressIn(12) => A12_nwv,
            WENegIn => WENeg_nwv,
            RASNegIn => RASNeg_nwv,
            CSNegIn => CSNeg_nwv,
            CASNegIn => CASNeg_nwv
        );

        -- Type definition for state machine
        TYPE mem_state IS (pwron,
                           precharge,
                           idle,
                           mode_set,
                           self_refresh,
                           self_refresh_rec,
                           auto_refresh,
                           pwrdwn,
                           bank_act,
                           bank_act_pwrdwn,
                           write,
                           write_suspend,
                           read,
                           read_suspend,
                           write_auto_pre,
                           read_auto_pre,
                           write_sec,
                           read_sec
                          );

        TYPE statebanktype IS array (hi_bank downto 0) of mem_state;

        SIGNAL statebank : statebanktype;
        SIGNAL next_statebank : statebanktype;

        SIGNAL CAS_Lat   : NATURAL RANGE 2 to 3 := 2;
        SIGNAL D_zd      : std_logic_vector(HiDataBit DOWNTO 0);
        SIGNAL LDQS_zd   : std_logic;
        SIGNAL UDQS_zd   : std_logic;

        SIGNAL DLL_EN    : boolean := false;
        SIGNAL DLL_reset : boolean := false;
        SIGNAL PERIOD    : time := 50 ns;       -- CLK period
        SIGNAL CLKint    : std_ulogic := '0';
        SIGNAL CLKtemp   : std_ulogic := '0';
        SIGNAL CLKcomb   : std_ulogic := '0';
        SIGNAL HalfPer   : Time := 0 ns;
        SIGNAL dlldelay  : Time := 0 ns;
        -----------------------------------------------------------------------
        SIGNAL clk_tmp1     : std_logic;
        SIGNAL clkneg_tmp1  : std_logic;
        SIGNAL clk_tmp2     : std_logic;
        SIGNAL clkneg_tmp2  : std_logic;

        SIGNAL CLKIn        : std_logic;
        SIGNAL CLKNegIn     : std_logic;

    BEGIN
    ---------------------------------------------------------------------------
    --delta cycle fix
    ---------------------------------------------------------------------------
    clk_tmp1    <= CLK_In ;
    clkneg_tmp1 <= CLKNeg_In;
    clk_tmp2    <= clk_tmp1;
    clkneg_tmp2 <= clkneg_tmp1;