mt46v16m16.vhd

vhdl cod for ram.For sp3e

--------------------------------------------------------------------------------
--  File Name: mt46v16m16.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 2002-2006 Free Model Foundry; http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--  MODIFICATION HISTORY:
--
--  version: |  author:     | mod date: | changes made:
--    V1.0    M.Marinkovic   02 Dec 16   Initial release
--    V1.1    R. Munden      03 MAR 15   Changed type of some _nwv signals to
--                                       satisfy ncvhdl
--    V1.2    R. Munden      03 MAR 22   Removed DM initialization requirement
--                                       Added CLK skew check
--    V1.3    R. Munden      03 MAR 25   Removed DM valid check added CSNeg nop
--    V1.4    R. Munden      03 JUN 13   Changed initialize values of some sigs
--                                       remove DM for reads, changed AR generic
--    V1.5    R. Munden      03 JUN 16   Changed DQS to not drive 'X'
--                                       adjusted CL=2 timing
--    V1.6    R. Munden      03 JUL 03   Fixed address problem in burst reads
--    V1.7    R. Munden      03 AUG 05   Fixed timing problem with tRCD
--    V1.8    R. Munden      03 OCT 10   Enhaced memory preload capability
--    V1.9    R. Munden      03 DEC 15   Fixed enhaced memory preload capability
--                                       Fixed write burst problem
--    V1.10   M.Marinkovic   03 Dec 29   Fixed DQS Latch (prior/at/after CLK
--                                       edge
--    v1.11   M.Marinkovic   04 Jan 15   Fixed row/column address width problem
--    v1.12   M.Marinkovic   04 Jan 26   Added memory access procedures
--    v1.13   A.Savic        04 Mar 19   DQS preamble burst interrupt bug fix
--                                       Precharge after WRITE - tRW violation
--                                       detect added
--    V1.14   R. Munden      04 Jul 21   Made error message for tWR more detailed
--    V1.15   R. Munden      04 Aug 23   Correct Detect_tWR_Violation
--                                       Added wrt_bank variable
--    V1.16   R. Munden      06 Jan 06   Correct Burst_Cnt on writes
--
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
--
--  Library:    RAM
--  Technology: CMOS
--  Part:       mt46v16m16
--
--  Description: 4M x 16 x 4Banks Double Data Rate SDRAM
--------------------------------------------------------------------------------
-- Note:
--  Required simulator resolution 10ps or less
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE STD.textio.ALL;
                USE IEEE.VITAL_timing.all;
                USE IEEE.VITAL_primitives.all;
LIBRARY FMF;    USE FMF.gen_utils.ALL;
                USE FMF.conversions.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY mt46v16m16 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_BA0                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_BA1                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_LDQS                : VitalDelayType01 := VitalZeroDelay01;
        tipd_UDQS                : VitalDelayType01 := VitalZeroDelay01;
        tipd_LDM                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_UDM                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ0                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ1                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ2                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ3                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ4                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ5                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ6                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ7                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ8                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ9                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ10                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ11                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ12                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ13                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ14                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ15                : VitalDelayType01 := VitalZeroDelay01;
        tipd_CLKNeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_CLK                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_CKE                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_A0                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A1                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A2                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A3                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A4                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A5                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A6                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A7                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A8                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A9                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A10                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_A11                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_A12                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_WENeg               : VitalDelayType01 := VitalZeroDelay01;
        tipd_RASNeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_CSNeg               : VitalDelayType01 := VitalZeroDelay01;
        tipd_CASNeg              : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_CLK_DQ0              : VitalDelayType01Z := UnitDelay01Z;
        -- Access window / 2
        tpd_CLK_DQ1              : VitalDelayType    := UnitDelay;
        -- tpw values: pulse widths
        tpw_CLK_posedge          : VitalDelayType    := UnitDelay;
        tpw_CLK_negedge          : VitalDelayType    := UnitDelay;
        tpw_LDQS_posedge          : VitalDelayType    := UnitDelay;
        -- tsetup values: setup times
        tsetup_A0_CLK            : VitalDelayType    := UnitDelay;
        tsetup_DQ0_CLK           : VitalDelayType    := UnitDelay;
        tsetup_LDQS_CLK          : VitalDelayType    := UnitDelay;
        tsetup_DQ0_LDQS          : VitalDelayType    := UnitDelay;
        tsetup_LDM_LDQS          : VitalDelayType    := UnitDelay;
        -- thold values: hold times
        thold_A0_CLK             : VitalDelayType    := UnitDelay;
        thold_DQ0_CLK            : VitalDelayType    := UnitDelay;
        thold_LDQS_CLK           : VitalDelayType    := UnitDelay;
        thold_DQ0_LDQS           : VitalDelayType    := UnitDelay;
        thold_LDM_LDQS           : VitalDelayType    := UnitDelay;
        -- tperiod_min: minimum clock period = 1/max freq
        tperiod_CLK_posedge      : VitalDelayType    := UnitDelay;
        -- tskew values: skew times
        tskew_CLK_CLKNeg         : VitalDelayType    := UnitDelay;
        -- tdevice values: values for internal delays (for the -6)
        tdevice_REF              : VitalDelayType    := 15_625 ns;
        tdevice_TRC              : VitalDelayType    := 60 ns;
        tdevice_TRCD             : VitalDelayType    := 18 ns;
        tdevice_TRP              : VitalDelayType    := 18 ns;
        tdevice_TRFC             : VitalDelayType    := 72 ns;
        tdevice_TWR              : VitalDelayType    := 15 ns;
        tdevice_TRAS             : VitalDelayType01  := (42 ns, 70_000 ns);
        -- tpowerup: Power up initialization time. Data sheets say 200 us.
        -- May be shortened during simulation debug.
        tpowerup            : TIME      := 2 us;
        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        SeverityMode        : SEVERITY_LEVEL := WARNING;
        -- memory file to be loaded
        mem_file_name       : STRING    :="none";
                                        --"mt46v16m16.mem";
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        BA0             : IN    std_logic := 'U';
        BA1             : IN    std_logic := 'U';
        LDM             : IN    std_logic := 'U';
        UDM             : IN    std_logic := 'U';
        LDQS            : INOUT std_logic := 'U';
        UDQS            : INOUT std_logic := 'U';
        DQ0             : INOUT std_logic := 'U';
        DQ1             : INOUT std_logic := 'U';
        DQ2             : INOUT std_logic := 'U';
        DQ3             : INOUT std_logic := 'U';
        DQ4             : INOUT std_logic := 'U';
        DQ5             : INOUT std_logic := 'U';
        DQ6             : INOUT std_logic := 'U';
        DQ7             : INOUT std_logic := 'U';
        DQ8             : INOUT std_logic := 'U';
        DQ9             : INOUT std_logic := 'U';
        DQ10            : INOUT std_logic := 'U';
        DQ11            : INOUT std_logic := 'U';
        DQ12            : INOUT std_logic := 'U';
        DQ13            : INOUT std_logic := 'U';
        DQ14            : INOUT std_logic := 'U';
        DQ15            : INOUT std_logic := 'U';
        CLK             : IN    std_logic := 'U';
        CLKNeg          : IN    std_logic := 'U';
        CKE             : IN    std_logic := 'U';
        A0              : IN    std_logic := 'U';
        A1              : IN    std_logic := 'U';
        A2              : IN    std_logic := 'U';
        A3              : IN    std_logic := 'U';
        A4              : IN    std_logic := 'U';
        A5              : IN    std_logic := 'U';
        A6              : IN    std_logic := 'U';
        A7              : IN    std_logic := 'U';
        A8              : IN    std_logic := 'U';
        A9              : IN    std_logic := 'U';
        A10             : IN    std_logic := 'U';
        A11             : IN    std_logic := 'U';
        A12             : IN    std_logic := 'U';
        WENeg           : IN    std_logic := 'U';
        RASNeg          : IN    std_logic := 'U';
        CSNeg           : IN    std_logic := 'U';
        CASNeg          : IN    std_logic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of mt46v16m16 : ENTITY IS TRUE;
END mt46v16m16;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of mt46v16m16 IS
    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    CONSTANT partID         : STRING := "mt46v16m16";
    CONSTANT hi_bank        : NATURAL := 3;
    CONSTANT HiAddrBit      : NATURAL := 12;
    CONSTANT HiColBit       : NATURAL := 8;
    CONSTANT HiDataBit      : NATURAL := 15;

    CONSTANT depth          : NATURAL := 16#3FFFFF#; --<< for simulation purpose
                                               -- real value is 16#3FFFFF#;

    SIGNAL CKEreg              : X01 := 'X';
    SIGNAL PoweredUp           : boolean := false;

    SIGNAL BA0_ipd             : std_ulogic := 'U';
    SIGNAL BA1_ipd             : std_ulogic := 'U';
    SIGNAL LDQS_ipd            : std_ulogic := 'U';
    SIGNAL UDQS_ipd            : std_ulogic := 'U';
    SIGNAL LDM_ipd             : std_ulogic := 'U';
    SIGNAL UDM_ipd             : std_ulogic := 'U';
    SIGNAL DQ0_ipd             : std_ulogic := 'U';
    SIGNAL DQ1_ipd             : std_ulogic := 'U';
    SIGNAL DQ2_ipd             : std_ulogic := 'U';
    SIGNAL DQ3_ipd             : std_ulogic := 'U';
    SIGNAL DQ4_ipd             : std_ulogic := 'U';
    SIGNAL DQ5_ipd             : std_ulogic := 'U';
    SIGNAL DQ6_ipd             : std_ulogic := 'U';
    SIGNAL DQ7_ipd             : std_ulogic := 'U';
    SIGNAL DQ8_ipd             : std_ulogic := 'U';
    SIGNAL DQ9_ipd             : std_ulogic := 'U';
    SIGNAL DQ10_ipd            : std_ulogic := 'U';
    SIGNAL DQ11_ipd            : std_ulogic := 'U';
    SIGNAL DQ12_ipd            : std_ulogic := 'U';
    SIGNAL DQ13_ipd            : std_ulogic := 'U';
    SIGNAL DQ14_ipd            : std_ulogic := 'U';
    SIGNAL DQ15_ipd            : std_ulogic := 'U';
    SIGNAL CLK_ipd             : std_ulogic := 'U';
    SIGNAL CLKNeg_ipd          : std_ulogic := 'U';
    SIGNAL CKE_ipd             : std_ulogic := 'U';
    SIGNAL A0_ipd              : std_ulogic := 'U';
    SIGNAL A1_ipd              : std_ulogic := 'U';
    SIGNAL A2_ipd              : std_ulogic := 'U';
    SIGNAL A3_ipd              : std_ulogic := 'U';
    SIGNAL A4_ipd              : std_ulogic := 'U';
    SIGNAL A5_ipd              : std_ulogic := 'U';
    SIGNAL A6_ipd              : std_ulogic := 'U';
    SIGNAL A7_ipd              : std_ulogic := 'U';
    SIGNAL A8_ipd              : std_ulogic := 'U';
    SIGNAL A9_ipd              : std_ulogic := 'U';
    SIGNAL A10_ipd             : std_ulogic := 'U';
    SIGNAL A11_ipd             : std_ulogic := 'U';
    SIGNAL A12_ipd             : std_ulogic := 'U';
    SIGNAL WENeg_ipd           : std_ulogic := 'U';
    SIGNAL RASNeg_ipd          : std_ulogic := 'U';
    SIGNAL CSNeg_ipd           : std_ulogic := 'U';
    SIGNAL CASNeg_ipd          : std_ulogic := 'U';

    SIGNAL BA0_nwv             : std_ulogic := 'U';
    SIGNAL BA1_nwv             : std_ulogic := 'U';
    SIGNAL LDQS_nwv            : std_ulogic := 'U';
    SIGNAL UDQS_nwv            : std_ulogic := 'U';
    SIGNAL LDM_nwv             : std_ulogic := 'U';
    SIGNAL UDM_nwv             : std_ulogic := 'U';
    SIGNAL DQ0_nwv             : UX01 := 'U';
    SIGNAL DQ1_nwv             : UX01 := 'U';
    SIGNAL DQ2_nwv             : UX01 := 'U';
    SIGNAL DQ3_nwv             : UX01 := 'U';
    SIGNAL DQ4_nwv             : UX01 := 'U';
    SIGNAL DQ5_nwv             : UX01 := 'U';
    SIGNAL DQ6_nwv             : UX01 := 'U';
    SIGNAL DQ7_nwv             : UX01 := 'U';
    SIGNAL DQ8_nwv             : UX01 := 'U';
    SIGNAL DQ9_nwv             : UX01 := 'U';
    SIGNAL DQ10_nwv            : UX01 := 'U';
    SIGNAL DQ11_nwv            : UX01 := 'U';
    SIGNAL DQ12_nwv            : UX01 := 'U';
    SIGNAL DQ13_nwv            : UX01 := 'U';
    SIGNAL DQ14_nwv            : UX01 := 'U';
    SIGNAL DQ15_nwv            : UX01 := 'U';
    SIGNAL A0_nwv              : UX01 := 'U';
    SIGNAL A1_nwv              : UX01 := 'U';
    SIGNAL A2_nwv              : UX01 := 'U';
    SIGNAL A3_nwv              : UX01 := 'U';
    SIGNAL A4_nwv              : UX01 := 'U';
    SIGNAL A5_nwv              : UX01 := 'U';
    SIGNAL A6_nwv              : UX01 := 'U';
    SIGNAL A7_nwv              : UX01 := 'U';
    SIGNAL A8_nwv              : UX01 := 'U';