idt709079.vhd

vhdl cod for ram.For sp3e

                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_CNTENRNegIn_CLKRIn,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_CNTENRNegIn_CLKRIn );

                VitalSetupHoldCheck (
                    TestSignal      => CNTRSTLNegIn,
                    TestSignalName  => "CNTRSTLNeg",
                    RefSignal       => CLKLIn,
                    RefSignalName   => "CLKL",
                    SetupHigh       => tsetup_CNTRSTLNeg_CLKL,
                    SetupLow        => tsetup_CNTRSTLNeg_CLKL,
                    HoldHigh        => thold_CNTRSTLNeg_CLKL,
                    HoldLow         => thold_CNTRSTLNeg_CLKL,
                    CheckEnabled    => (CE0LNeg_nwv ='0' AND CE1L_nwv = '1'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_CNTRSTLNegIn_CLKLIn,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_CNTRSTLNegIn_CLKLIn );

                VitalSetupHoldCheck (
                    TestSignal      => CNTRSTRNegIn,
                    TestSignalName  => "CNTRSTRNeg",
                    RefSignal       => CLKRIn,
                    RefSignalName   => "CLKR",
                    SetupHigh       => tsetup_CNTRSTLNeg_CLKL,
                    SetupLow        => tsetup_CNTRSTLNeg_CLKL,
                    HoldHigh        => thold_CNTRSTLNeg_CLKL,
                    HoldLow         => thold_CNTRSTLNeg_CLKL,
                    CheckEnabled    => (CE0RNeg_nwv ='0' AND CE1R_nwv = '1'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_CNTRSTRNegIn_CLKRIn,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_CNTRSTRNegIn_CLKRIn );

                VitalSetupHoldCheck (
                    TestSignal      => CLKLIn,
                    TestSignalName  => "CLKL",
                    RefSignal       => CLKRIn,
                    RefSignalName   => "CLKR",
                    SetupHigh       => tsetup_CLKR_CLKL,
                    CheckEnabled    => (RWLIn = '0' AND ALIn = ARIn
                                        AND PIPERIn = '0'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_CLKRIn_CLKLIn,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_CLKRIn_CLKLIn );

                VitalPeriodPulseCheck (
                  TestSignal      =>  CLKLIn,
                  TestSignalName  =>  "CLKL",
                  Period          =>  tperiod_CLKR_PIPER_EQ_1_posedge,
                  PulseWidthLow   =>  tpw_CLKR_PIPER_EQ_1_negedge,
                  PulseWidthHigh  =>  tpw_CLKR_PIPER_EQ_1_posedge,
                  PeriodData      =>  TD_CLKLIn,
                  XOn             =>  XOn,
                  MsgOn           =>  MsgOn,
                  HeaderMsg       =>  InstancePath & PartID,
                  CheckEnabled    =>  TRUE,
                  Violation       =>  Pviol_CLKLIn );

                VitalPeriodPulseCheck (
                  TestSignal      =>  CLKRIn,
                  TestSignalName  =>  "CLKR",
                  Period          =>  tperiod_CLKR_PIPER_EQ_1_posedge,
                  PulseWidthLow   =>  tpw_CLKR_PIPER_EQ_1_negedge,
                  PulseWidthHigh  =>  tpw_CLKR_PIPER_EQ_1_posedge,
                  PeriodData      =>  TD_CLKRIn,
                  XOn             =>  XOn,
                  MsgOn           =>  MsgOn,
                  HeaderMsg       =>  InstancePath & PartID,
                  CheckEnabled    =>  (PIPER_nwv = '1'),
                  Violation       =>  Pviol_CLKRIn );

                VitalPeriodPulseCheck (
                  TestSignal      =>  CLKRIn,
                  TestSignalName  =>  "CLKR",
                  Period          =>  tperiod_CLKR_PIPER_EQ_0_posedge,
                  PulseWidthLow   =>  tpw_CLKR_PIPER_EQ_0_negedge,
                  PulseWidthHigh  =>  tpw_CLKR_PIPER_EQ_0_posedge,
                  PeriodData      =>  TD_CLKRIn,
                  XOn             =>  XOn,
                  MsgOn           =>  MsgOn,
                  HeaderMsg       =>  InstancePath & PartID,
                  CheckEnabled    =>  (PIPER_nwv = '0'),
                  Violation       =>  Pviol_CLKRIn );

               Violation := Tviol_ALIn_CLKLIn OR Tviol_ARIn_CLKRIn OR
                            Tviol_CE0LNegIn_CLKLIn OR Tviol_CE0RNegIn_CLKRIn OR
                            Tviol_CE1LIn_CLKLIn OR Tviol_CE1RIn_CLKRIn OR
                            Tviol_RWLIn_CLKLIn OR Tviol_RWRIn_CLKRIn OR
                            Tviol_IOLIn_CLKLIn OR Tviol_IORIn_CLKRIn OR
                            Tviol_ADSLNegIn_CLKLIn OR Tviol_ADSRNegIn_CLKRIn OR
                            Tviol_CNTENLNegIn_CLKLIn OR Tviol_CNTENRNegIn_CLKRIn
                            OR Tviol_CNTRSTLNegIn_CLKLIn OR
                            Tviol_CNTRSTRNegIn_CLKRIn OR Pviol_CLKLIn OR
                            Pviol_CLKRIn;

            END IF; -- Timing Check Section

            --------------------------------------------------------------------
            -- Functional Section
            --------------------------------------------------------------------

            IF rising_edge(CLKLIn) THEN

                IF RWL_nwv = '1' THEN    -- read pipeline
                    IF DataTempL >= 0 THEN
                        DataLTmp := To_slv(DataTempL, DataWidth);
                    ELSIF DataTempL = -2 THEN
                        DataLTmp := (OTHERS => 'U');
                    ELSE
                        DataLTmp := (OTHERS => 'X');
                    END IF;
                    IF LatencyL THEN
                        DataLTmp := (OTHERS => 'Z');
                    END IF;
                    LatencyL := false;
                END IF;

                IF CE0LNeg_nwv = '0' AND CE1L_nwv = '1' THEN
                    IF CNTRSTLNeg_nwv = '0' THEN      -- reset addr
                        LocationL := 0;
                    ELSIF ADSLNeg_nwv = '0' THEN      -- load addr
                        LocationL := To_Nat(ALIn);
                    ELSIF CNTENLNeg_nwv = '0' THEN
                        IF LocationL < TotalLOC THEN  -- inc addr
                            LocationL := LocationL + 1;
                        ELSE
                            LocationL := 0;
                        END IF;
                    END IF;

                    IF RWL_nwv = '1' THEN                -- read
                        DataTempL := MemData(LocationL);
                    ELSE                                 -- write
                        DataLTmp := (OTHERS => 'Z');
                        LatencyL := true;
                        IF Violation = '0' THEN
                            MemData(LocationL) := To_Nat(IOLIn);
                        ELSE
                            MemData(LocationL) := -1;
                            WrtDataL := -1;
                        END IF;
                    END IF;
                END IF;
            END IF;

            IF rising_edge(CLKRIn) THEN

                IF Tviol_CLKRIn_CLKLin = 'X' THEN
                    Addr_Match <= true;
                ELSE
                    Addr_Match <= false;
                END IF;

                IF RWR_nwv = '1' AND PIPERIn = '1' THEN     -- read pipeline
                    IF DataTempR >= 0 THEN
                        DataRtmp := To_slv(DataTempR, DataWidth);
                    ELSIF DataTempR = -2 THEN
                        DataRtmp := (OTHERS => 'U');
                    ELSE
                        DataRtmp := (OTHERS => 'X');
                    END IF;
                    IF LatencyR THEN
                        DataRtmp := (OTHERS => 'Z');
                    END IF;
                    LatencyR := false;
                END IF;

                IF CE0RNeg_nwv = '0' AND CE1R_nwv = '1' THEN
                    IF CNTRSTRNeg_nwv = '0' THEN      -- reset addr
                        LocationR := 0;
                    ELSIF ADSRNeg_nwv = '0' THEN      -- load addr
                        LocationR := To_Nat(ARIn);
                    ELSIF CNTENRNeg_nwv = '0' THEN
                        IF LocationR < TotalLOC THEN  -- inc addr
                            LocationR := LocationR + 1;
                        ELSE
                            LocationR := 0;
                        END IF;
                    END IF;

                    IF RWR_nwv = '1' THEN                -- read
                        DataTempR := MemData(LocationR);
                        IF PIPERIn = '0' THEN
                            IF DataTempR >= 0 THEN
                                DataRtmp := To_slv(DataTempR, DataWidth);
                            ELSIF DataTempR = -2 THEN
                                DataRtmp := (OTHERS => 'U');
                            ELSE
                                DataRtmp := (OTHERS => 'X');
                            END IF;
                        END IF;
                    ELSE                                 -- write
                        DataRtmp := (OTHERS => 'Z');
                        LatencyR := true;
                        IF Violation = '0' THEN
                            MemData(LocationR) := To_Nat(IORIn);
                        ELSE
                            MemData(LocationR) := -1;
                            WrtDataR := -1;
                        END IF;
                    END IF;
                END IF;
            END IF;

            IF (OELNeg_nwv = '1') THEN
                DataLDrive := (OTHERS => 'Z');
            ELSE
                DataLDrive := DataLTmp;
            END IF;

            IF (OERNeg_nwv = '1') THEN
                DataRDrive := (OTHERS => 'Z');
            ELSE
                DataRDrive := DataRTmp;
            END IF;

            IOL_zd <= DataLDrive;
            IOR_zd <= DataRDrive;

        END PROCESS;

        ------------------------------------------------------------------------
        -- Path Delay Processes generated as a function of data width
        ------------------------------------------------------------------------
        DataOut_Width : FOR i IN HiDbit DOWNTO 0 GENERATE
            DataOut_Delay : PROCESS (IOR_zd(i), IOL_zd(i))
              VARIABLE IOR_GlitchData:VitalGlitchDataArrayType(HiDbit Downto 0);
              VARIABLE IOL_GlitchData:VitalGlitchDataArrayType(HiDbit Downto 0);
            BEGIN
                VitalPathDelay01Z (
                    OutSignal       => IOLOut(i),
                    OutSignalName   => "IOL",
                    OutTemp         => IOL_zd(i),
                    Mode            => OnEvent,
                    GlitchData      => IOL_GlitchData(i),
                    Paths           => (
                        0 => (InputChangeTime => OELNegIn'LAST_EVENT,
                              PathDelay       => tpd_OELNeg_IOL0,
                              PathCondition   => TRUE),
                        1 => (InputChangeTime => CLKLIn'LAST_EVENT,
                              PathDelay       => tpd_CLKR_IOR0_PIPER_EQ_1,
                              PathCondition   => TRUE)
                   )
               );

                VitalPathDelay01Z (
                    OutSignal       => IOROut(i),
                    OutSignalName   => "IOR",
                    OutTemp         => IOR_zd(i),
                    Mode            => OnEvent,
                    GlitchData      => IOR_GlitchData(i),
                    Paths           => (
                        0 => (InputChangeTime => OERNegIn'LAST_EVENT,
                              PathDelay       => tpd_OELNeg_IOL0,
                              PathCondition   => TRUE),
                        1 => (InputChangeTime => CLKRIn'LAST_EVENT,
                              PathDelay       => tpd_CLKR_IOR0_PIPER_EQ_1,
                              PathCondition   => (PIPERIn = '1')),
                        2 => (InputChangeTime => CLKRIn'LAST_EVENT,
                              PathDelay       => tpd_CLKR_IOR0_PIPER_EQ_0,
                              PathCondition   => (PIPERIn = '0' AND 
                                                  not Addr_Match)),
                        3 => (InputChangeTime => CLKLIn'LAST_EVENT,
                              PathDelay       => tpd_CLKL_IOR0,
                              PathCondition   => Addr_Match)
                   )
               );

            END PROCESS;
        END GENERATE;

    END BLOCK;
END vhdl_behavioral;