idt709079.vhd

vhdl cod for ram.For sp3e

    SIGNAL AR12_ipd            : std_ulogic := 'U';
    SIGNAL AR13_ipd            : std_ulogic := 'U';
    SIGNAL AR14_ipd            : std_ulogic := 'U';
    SIGNAL AL0_ipd             : std_ulogic := 'U';
    SIGNAL AL1_ipd             : std_ulogic := 'U';
    SIGNAL AL2_ipd             : std_ulogic := 'U';
    SIGNAL AL3_ipd             : std_ulogic := 'U';
    SIGNAL AL4_ipd             : std_ulogic := 'U';
    SIGNAL AL5_ipd             : std_ulogic := 'U';
    SIGNAL AL6_ipd             : std_ulogic := 'U';
    SIGNAL AL7_ipd             : std_ulogic := 'U';
    SIGNAL AL8_ipd             : std_ulogic := 'U';
    SIGNAL AL9_ipd             : std_ulogic := 'U';
    SIGNAL AL10_ipd            : std_ulogic := 'U';
    SIGNAL AL11_ipd            : std_ulogic := 'U';
    SIGNAL AL12_ipd            : std_ulogic := 'U';
    SIGNAL AL13_ipd            : std_ulogic := 'U';
    SIGNAL AL14_ipd            : std_ulogic := 'U';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1 : VitalWireDelay (RWR_ipd, RWR, tipd_RWR);
        w_2 : VitalWireDelay (RWL_ipd, RWL, tipd_RWL);
        w_3 : VitalWireDelay (CE1R_ipd, CE1R, tipd_CE1R);
        w_4 : VitalWireDelay (CE1L_ipd, CE1L, tipd_CE1L);
        w_5 : VitalWireDelay (PIPER_ipd, PIPER, tipd_PIPER);
        w_6 : VitalWireDelay (CLKR_ipd, CLKR, tipd_CLKR);
        w_7 : VitalWireDelay (CLKL_ipd, CLKL, tipd_CLKL);
        w_8 : VitalWireDelay (CNTENRNeg_ipd, CNTENRNeg, tipd_CNTENRNeg);
        w_9 : VitalWireDelay (CNTENLNeg_ipd, CNTENLNeg, tipd_CNTENLNeg);
        w_10 : VitalWireDelay (CNTRSTRNeg_ipd, CNTRSTRNeg, tipd_CNTRSTRNeg);
        w_11 : VitalWireDelay (CNTRSTLNeg_ipd, CNTRSTLNeg, tipd_CNTRSTLNeg);
        w_12 : VitalWireDelay (ADSRNeg_ipd, ADSRNeg, tipd_ADSRNeg);
        w_13 : VitalWireDelay (ADSLNeg_ipd, ADSLNeg, tipd_ADSLNeg);
        w_14 : VitalWireDelay (CE0RNeg_ipd, CE0RNeg, tipd_CE0RNeg);
        w_15 : VitalWireDelay (CE0LNeg_ipd, CE0LNeg, tipd_CE0LNeg);
        w_16 : VitalWireDelay (OERNeg_ipd, OERNeg, tipd_OERNeg);
        w_17 : VitalWireDelay (OELNeg_ipd, OELNeg, tipd_OELNeg);
        w_20 : VitalWireDelay (AR0_ipd, AR0, tipd_AR0);
        w_21 : VitalWireDelay (AR1_ipd, AR1, tipd_AR1);
        w_22 : VitalWireDelay (AR2_ipd, AR2, tipd_AR2);
        w_23 : VitalWireDelay (AR3_ipd, AR3, tipd_AR3);
        w_24 : VitalWireDelay (AR4_ipd, AR4, tipd_AR4);
        w_25 : VitalWireDelay (AR5_ipd, AR5, tipd_AR5);
        w_26 : VitalWireDelay (AR6_ipd, AR6, tipd_AR6);
        w_27 : VitalWireDelay (AR7_ipd, AR7, tipd_AR7);
        w_28 : VitalWireDelay (AR8_ipd, AR8, tipd_AR8);
        w_29 : VitalWireDelay (AR9_ipd, AR9, tipd_AR9);
        w_30 : VitalWireDelay (AR10_ipd, AR10, tipd_AR10);
        w_31 : VitalWireDelay (AR11_ipd, AR11, tipd_AR11);
        w_32 : VitalWireDelay (AR12_ipd, AR12, tipd_AR12);
        w_33 : VitalWireDelay (AR13_ipd, AR13, tipd_AR13);
        w_34 : VitalWireDelay (AR14_ipd, AR14, tipd_AR14);
        w_37 : VitalWireDelay (AL0_ipd, AL0, tipd_AL0);
        w_38 : VitalWireDelay (AL1_ipd, AL1, tipd_AL1);
        w_39 : VitalWireDelay (AL2_ipd, AL2, tipd_AL2);
        w_40 : VitalWireDelay (AL3_ipd, AL3, tipd_AL3);
        w_41 : VitalWireDelay (AL4_ipd, AL4, tipd_AL4);
        w_42 : VitalWireDelay (AL5_ipd, AL5, tipd_AL5);
        w_43 : VitalWireDelay (AL6_ipd, AL6, tipd_AL6);
        w_44 : VitalWireDelay (AL7_ipd, AL7, tipd_AL7);
        w_45 : VitalWireDelay (AL8_ipd, AL8, tipd_AL8);
        w_46 : VitalWireDelay (AL9_ipd, AL9, tipd_AL9);
        w_47 : VitalWireDelay (AL10_ipd, AL10, tipd_AL10);
        w_48 : VitalWireDelay (AL11_ipd, AL11, tipd_AL11);
        w_49 : VitalWireDelay (AL12_ipd, AL12, tipd_AL12);
        w_50 : VitalWireDelay (AL13_ipd, AL13, tipd_AL13);
        w_51 : VitalWireDelay (AL14_ipd, AL14, tipd_AL14);
        w_53 : VitalWireDelay (IOR7_ipd, IOR7, tipd_IOR7);
        w_54 : VitalWireDelay (IOR6_ipd, IOR6, tipd_IOR6);
        w_55 : VitalWireDelay (IOR5_ipd, IOR5, tipd_IOR5);
        w_56 : VitalWireDelay (IOR4_ipd, IOR4, tipd_IOR4);
        w_57 : VitalWireDelay (IOR3_ipd, IOR3, tipd_IOR3);
        w_58 : VitalWireDelay (IOR2_ipd, IOR2, tipd_IOR2);
        w_59 : VitalWireDelay (IOR1_ipd, IOR1, tipd_IOR1);
        w_60 : VitalWireDelay (IOR0_ipd, IOR0, tipd_IOR0);
        w_61 : VitalWireDelay (IOL7_ipd, IOL7, tipd_IOL7);
        w_62 : VitalWireDelay (IOL6_ipd, IOL6, tipd_IOL6);
        w_63 : VitalWireDelay (IOL5_ipd, IOL5, tipd_IOL5);
        w_64 : VitalWireDelay (IOL4_ipd, IOL4, tipd_IOL4);
        w_65 : VitalWireDelay (IOL3_ipd, IOL3, tipd_IOL3);
        w_66 : VitalWireDelay (IOL2_ipd, IOL2, tipd_IOL2);
        w_67 : VitalWireDelay (IOL1_ipd, IOL1, tipd_IOL1);
        w_68 : VitalWireDelay (IOL0_ipd, IOL0, tipd_IOL0);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Main Behavior Block
    ----------------------------------------------------------------------------
    Behavior: BLOCK

        PORT (
            ALIn         : IN    std_logic_vector(HiAbit downto 0);
            ARIn         : IN    std_logic_vector(HiAbit downto 0);
            IOLIn        : IN    std_logic_vector(HiDbit downto 0);
            IORIn        : IN    std_logic_vector(HiDbit downto 0);
            IOLOut       : OUT   std_logic_vector(HiDbit downto 0);
            IOROut       : OUT   std_logic_vector(HiDbit downto 0);
            RWLIn        : IN    std_ulogic := 'U';
            RWRIn        : IN    std_ulogic := 'U';
            OELNegIn     : IN    std_ulogic := 'U';
            OERNegIn     : IN    std_ulogic := 'U';
            CE0LNegIn    : IN    std_ulogic := 'U';
            CE0RNegIn    : IN    std_ulogic := 'U';
            CE1LIn       : IN    std_ulogic := 'U';
            CE1RIn       : IN    std_ulogic := 'U';
            CLKLIn       : IN    std_ulogic := 'U';
            CLKRIn       : IN    std_ulogic := 'U';
            CNTRSTLNegIn : IN    std_ulogic := 'U';
            CNTRSTRNegIn : IN    std_ulogic := 'U';
            CNTENRNegIn  : IN    std_ulogic := 'U';
            CNTENLNegIn  : IN    std_ulogic := 'U';
            ADSRNegIn    : IN    std_ulogic := 'U';
            ADSLNegIn    : IN    std_ulogic := 'U';
            PIPERIn      : IN    std_ulogic := '1'
        );
        PORT MAP (
            ALIn(0) =>  AL0_ipd,
            ALIn(1) =>  AL1_ipd,
            ALIn(2) =>  AL2_ipd,
            ALIn(3) =>  AL3_ipd,
            ALIn(4) =>  AL4_ipd,
            ALIn(5) =>  AL5_ipd,
            ALIn(6) =>  AL6_ipd,
            ALIn(7) =>  AL7_ipd,
            ALIn(8) =>  AL8_ipd,
            ALIn(9) =>  AL9_ipd,
            ALIn(10) =>  AL10_ipd,
            ALIn(11) =>  AL11_ipd,
            ALIn(12) =>  AL12_ipd,
            ALIn(13) =>  AL13_ipd,
            ALIn(14) =>  AL14_ipd,
            ARIn(0) =>  AR0_ipd,
            ARIn(1) =>  AR1_ipd,
            ARIn(2) =>  AR2_ipd,
            ARIn(3) =>  AR3_ipd,
            ARIn(4) =>  AR4_ipd,
            ARIn(5) =>  AR5_ipd,
            ARIn(6) =>  AR6_ipd,
            ARIn(7) =>  AR7_ipd,
            ARIn(8) =>  AR8_ipd,
            ARIn(9) =>  AR9_ipd,
            ARIn(10) =>  AR10_ipd,
            ARIn(11) =>  AR11_ipd,
            ARIn(12) =>  AR12_ipd,
            ARIn(13) =>  AR13_ipd,
            ARIn(14) =>  AR14_ipd,
            IOLIn(0) => IOL0_ipd,
            IOLIn(1) => IOL1_ipd,
            IOLIn(2) => IOL2_ipd,
            IOLIn(3) => IOL3_ipd,
            IOLIn(4) => IOL4_ipd,
            IOLIn(5) => IOL5_ipd,
            IOLIn(6) => IOL6_ipd,
            IOLIn(7) => IOL7_ipd,
            IORIn(0) => IOR0_ipd,
            IORIn(1) => IOR1_ipd,
            IORIn(2) => IOR2_ipd,
            IORIn(3) => IOR3_ipd,
            IORIn(4) => IOR4_ipd,
            IORIn(5) => IOR5_ipd,
            IORIn(6) => IOR6_ipd,
            IORIn(7) => IOR7_ipd,
            IOLOut(0) => IOL0,
            IOLOut(1) => IOL1,
            IOLOut(2) => IOL2,
            IOLOut(3) => IOL3,
            IOLOut(4) => IOL4,
            IOLOut(5) => IOL5,
            IOLOut(6) => IOL6,
            IOLOut(7) => IOL7,
            IOROut(0) => IOR0,
            IOROut(1) => IOR1,
            IOROut(2) => IOR2,
            IOROut(3) => IOR3,
            IOROut(4) => IOR4,
            IOROut(5) => IOR5,
            IOROut(6) => IOR6,
            IOROut(7) => IOR7,
            RWLIn     => RWL_ipd,
            RWRIn     => RWR_ipd,
            OELNegIn  => OELNeg_ipd,
            OERNegIn  => OERNeg_ipd,
            CE0LNegIn  => CE0LNeg_ipd,
            CE0RNegIn  => CE0RNeg_ipd,
            CE1LIn  => CE1L_ipd,
            CE1RIn  => CE1R_ipd,
            CLKLIn  => CLKL_ipd,
            CLKRIn  => CLKR_ipd,
            CNTRSTLNegIn  => CNTRSTLNeg_ipd,
            CNTRSTRNegIn  => CNTRSTRNeg_ipd,
            CNTENRNegIn  => CNTENRNeg_ipd,
            CNTENLNegIn  => CNTENLNeg_ipd,
            ADSRNegIn  => ADSRNeg_ipd,
            ADSLNegIn  => ADSLNeg_ipd,
            PIPERIn   => PIPER_ipd
        );

        SIGNAL IOL_zd    : std_logic_vector(HiDbit DOWNTO 0);
        SIGNAL IOR_zd    : std_logic_vector(HiDbit DOWNTO 0);
        SIGNAL Addr_Match : boolean;

    BEGIN
        ------------------------------------------------------------------------
        -- Behavior Process
        ------------------------------------------------------------------------
        Memory : PROCESS (OELNegIn, OERNegIn, RWLIn, RWRIn, CE0LNegIn, CE0RNegIn,
                          ALIn, ARIn, IOLIn, IORIn, CE1LIn, CE1RIn, CLKLIn,
                          CLKRIn, CNTRSTLNegIn, CNTRSTRNegIn, CNTENRNegIn,
                          CNTENLNegIn, ADSRNegIn, ADSLNegIn, PIPERIn)

            -- Timing Check Variables
            VARIABLE Tviol_ALIn_CLKLIn         : X01 := '0';
            VARIABLE TD_ALIn_CLKLIn            : VitalTimingDataType;

            VARIABLE Tviol_ARIn_CLKRIn         : X01 := '0';
            VARIABLE TD_ARIn_CLKRIn            : VitalTimingDataType;

            VARIABLE Tviol_CE0LNegIn_CLKLIn    :  X01 := '0';
            VARIABLE TD_CE0LNegIn_CLKLIn       : VitalTimingDataType;

            VARIABLE Tviol_CE0RNegIn_CLKRIn    :  X01 := '0';
            VARIABLE TD_CE0RNegIn_CLKRIn       : VitalTimingDataType;

            VARIABLE Tviol_CE1LIn_CLKLIn       :  X01 := '0';
            VARIABLE TD_CE1LIn_CLKLIn          : VitalTimingDataType;

            VARIABLE Tviol_CE1RIn_CLKRIn       :  X01 := '0';
            VARIABLE TD_CE1RIn_CLKRIn          : VitalTimingDataType;

            VARIABLE Tviol_RWLIn_CLKLIn        : X01 := '0';
            VARIABLE TD_RWLIn_CLKLIn           : VitalTimingDataType;

            VARIABLE Tviol_RWRIn_CLKRIn        : X01 := '0';
            VARIABLE TD_RWRIn_CLKRIn           : VitalTimingDataType;

            VARIABLE Tviol_IOLIn_CLKLIn        : X01 := '0';
            VARIABLE TD_IOLIn_CLKLIn           : VitalTimingDataType;

            VARIABLE Tviol_IORIn_CLKRIn        : X01 := '0';
            VARIABLE TD_IORIn_CLKRIn           : VitalTimingDataType;

            VARIABLE Tviol_ADSLNegIn_CLKLIn    :  X01 := '0';
            VARIABLE TD_ADSLNegIn_CLKLIn       : VitalTimingDataType;

            VARIABLE Tviol_ADSRNegIn_CLKRIn    :  X01 := '0';
            VARIABLE TD_ADSRNegIn_CLKRIn       : VitalTimingDataType;

            VARIABLE Tviol_CNTENLNegIn_CLKLIn  :  X01 := '0';
            VARIABLE TD_CNTENLNegIn_CLKLIn     : VitalTimingDataType;

            VARIABLE Tviol_CNTENRNegIn_CLKRIn  :  X01 := '0';
            VARIABLE TD_CNTENRNegIn_CLKRIn     : VitalTimingDataType;

            VARIABLE Tviol_CNTRSTLNegIn_CLKLIn :  X01 := '0';
            VARIABLE TD_CNTRSTLNegIn_CLKLIn    : VitalTimingDataType;

            VARIABLE Tviol_CNTRSTRNegIn_CLKRIn :  X01 := '0';
            VARIABLE TD_CNTRSTRNegIn_CLKRIn    : VitalTimingDataType;

            VARIABLE Tviol_CLKRIn_CLKLIn       :  X01 := '0';
            VARIABLE TD_CLKRIn_CLKLIn          : VitalTimingDataType;

            VARIABLE Pviol_CLKLIn              :  X01 := '0';
            VARIABLE TD_CLKLIn     : VitalPeriodDataType := VitalPeriodDataInit;

            VARIABLE Pviol_CLKRIn              :  X01 := '0';
            VARIABLE TD_CLKRIn     : VitalPeriodDataType := VitalPeriodDataInit;

            -- Functionality Results Variables
            VARIABLE Violation  : X01 := '0';

            -- Memory array declaration
            TYPE MemStore IS ARRAY (0 to TotalLOC) OF INTEGER
                             RANGE  -2 TO MaxData;

            VARIABLE DataLDrive : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE DataRDrive : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE DataLtmp   : std_logic_vector(HiDbit DOWNTO 0)