idt709079.vhd

vhdl cod for ram.For sp3e

--------------------------------------------------------------------------------
--  File Name: idt709079.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 2000 Free Model Foundry; http://www.FreeModelFoundry.com
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--  MODIFICATION HISTORY:
-- 
--  version: |  author:  | mod date: | changes made:
--    V1.0    R. Munden    00 Oct 24   Initial release
-- 
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
-- 
--  Library:    RAM
--  Technology: CMOS
--  Part:       IDT709079
-- 
--  Description: Sync Pipelined Dual-Port SRAM 32K x 8
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;
                USE FMF.conversions.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY idt709079 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_RWR                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_RWL                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_CE1R                : VitalDelayType01 := VitalZeroDelay01;
        tipd_CE1L                : VitalDelayType01 := VitalZeroDelay01;
        tipd_PIPER               : VitalDelayType01 := VitalZeroDelay01;
        tipd_CLKR                : VitalDelayType01 := VitalZeroDelay01;
        tipd_CLKL                : VitalDelayType01 := VitalZeroDelay01;
        tipd_CNTENRNeg           : VitalDelayType01 := VitalZeroDelay01;
        tipd_CNTENLNeg           : VitalDelayType01 := VitalZeroDelay01;
        tipd_CNTRSTRNeg          : VitalDelayType01 := VitalZeroDelay01;
        tipd_CNTRSTLNeg          : VitalDelayType01 := VitalZeroDelay01;
        tipd_ADSRNeg             : VitalDelayType01 := VitalZeroDelay01;
        tipd_ADSLNeg             : VitalDelayType01 := VitalZeroDelay01;
        tipd_CE0RNeg             : VitalDelayType01 := VitalZeroDelay01;
        tipd_CE0LNeg             : VitalDelayType01 := VitalZeroDelay01;
        tipd_OERNeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_OELNeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOR7                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOR6                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOR5                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOR4                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOR3                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOR2                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOR1                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOR0                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOL7                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOL6                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOL5                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOL4                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOL3                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOL2                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOL1                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOL0                : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR0                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR1                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR2                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR3                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR4                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR5                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR6                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR7                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR8                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR9                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR10                : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR11                : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR12                : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR13                : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR14                : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL0                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL1                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL2                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL3                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL4                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL5                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL6                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL7                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL8                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL9                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL10                : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL11                : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL12                : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL13                : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL14                : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        -- tOE, tOLZ, tOHZ
        tpd_OELNeg_IOL0          : VitalDelayType01Z := UnitDelay01Z;
        -- tCD1, tCKHZ, tCKLZ
        tpd_CLKR_IOR0_PIPER_EQ_0 : VitalDelayType01Z := UnitDelay01Z;
        -- tCD2, tCKHZ, tCKLZ
        tpd_CLKR_IOR0_PIPER_EQ_1 : VitalDelayType01Z := UnitDelay01Z;
        -- tCWDD
        tpd_CLKL_IOR0            : VitalDelayType01Z := UnitDelay01Z;
        -- tpw values: pulse widths
        -- tLC1
        tpw_CLKR_PIPER_EQ_0_negedge     : VitalDelayType    := UnitDelay;
        -- tHC1
        tpw_CLKR_PIPER_EQ_0_posedge     : VitalDelayType    := UnitDelay;
        -- tLC2
        tpw_CLKR_PIPER_EQ_1_negedge     : VitalDelayType    := UnitDelay;
        -- tHC2
        tpw_CLKR_PIPER_EQ_1_posedge     : VitalDelayType    := UnitDelay;
        -- tperiod_min: minimum clock period = 1/max freq
        -- tCYC1
        tperiod_CLKR_PIPER_EQ_0_posedge : VitalDelayType := UnitDelay;
        -- tCYC2
        tperiod_CLKR_PIPER_EQ_1_posedge : VitalDelayType := UnitDelay;
        -- tsetup values: setup times
        -- tSA
        tsetup_AL0_CLKL          : VitalDelayType    := UnitDelay;
        -- tSC
        tsetup_CE1L_CLKL         : VitalDelayType    := UnitDelay;
        -- tSW
        tsetup_RWL_CLKL          : VitalDelayType    := UnitDelay;
        -- tSD
        tsetup_IOL0_CLKL         : VitalDelayType    := UnitDelay;
        -- tSAD
        tsetup_ADSLNeg_CLKL      : VitalDelayType    := UnitDelay;
        -- tSCN
        tsetup_CNTENLNeg_CLKL    : VitalDelayType    := UnitDelay;
        -- tSRST
        tsetup_CNTRSTLNeg_CLKL   : VitalDelayType    := UnitDelay;
        -- tCCS
        tsetup_CLKR_CLKL         : VitalDelayType    := UnitDelay;
        -- thold values: hold times
        -- tHA
        thold_AL0_CLKL           : VitalDelayType    := UnitDelay;
        -- tHC
        thold_CE1L_CLKL          : VitalDelayType    := UnitDelay;
        -- tHW
        thold_RWL_CLKL           : VitalDelayType    := UnitDelay;
        -- tHD
        thold_IOL0_CLKL          : VitalDelayType    := UnitDelay;
        -- tHAD
        thold_ADSLNeg_CLKL       : VitalDelayType    := UnitDelay;
        -- tHCN
        thold_CNTENLNeg_CLKL     : VitalDelayType    := UnitDelay;
        -- tHRST
        thold_CNTRSTLNeg_CLKL    : VitalDelayType    := UnitDelay;
        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        RWR             : IN    std_ulogic := 'U';
        RWL             : IN    std_ulogic := 'U';
        CE1R            : IN    std_ulogic := 'U';
        CE1L            : IN    std_ulogic := 'U';
        PIPER           : IN    std_ulogic := 'U';
        CLKR            : IN    std_ulogic := 'U';
        CLKL            : IN    std_ulogic := 'U';
        CNTENRNeg       : IN    std_ulogic := 'U';
        CNTENLNeg       : IN    std_ulogic := 'U';
        CNTRSTRNeg      : IN    std_ulogic := 'U';
        CNTRSTLNeg      : IN    std_ulogic := 'U';
        ADSRNeg         : IN    std_ulogic := 'U';
        ADSLNeg         : IN    std_ulogic := 'U';
        CE0RNeg         : IN    std_ulogic := 'U';
        CE0LNeg         : IN    std_ulogic := 'U';
        OERNeg          : IN    std_ulogic := 'U';
        OELNeg          : IN    std_ulogic := 'U';
        IOR7            : INOUT std_ulogic := 'U';
        IOR6            : INOUT std_ulogic := 'U';
        IOR5            : INOUT std_ulogic := 'U';
        IOR4            : INOUT std_ulogic := 'U';
        IOR3            : INOUT std_ulogic := 'U';
        IOR2            : INOUT std_ulogic := 'U';
        IOR1            : INOUT std_ulogic := 'U';
        IOR0            : INOUT std_ulogic := 'U';
        IOL7            : INOUT std_ulogic := 'U';
        IOL6            : INOUT std_ulogic := 'U';
        IOL5            : INOUT std_ulogic := 'U';
        IOL4            : INOUT std_ulogic := 'U';
        IOL3            : INOUT std_ulogic := 'U';
        IOL2            : INOUT std_ulogic := 'U';
        IOL1            : INOUT std_ulogic := 'U';
        IOL0            : INOUT std_ulogic := 'U';
        AR0             : IN    std_ulogic := 'U';
        AR1             : IN    std_ulogic := 'U';
        AR2             : IN    std_ulogic := 'U';
        AR3             : IN    std_ulogic := 'U';
        AR4             : IN    std_ulogic := 'U';
        AR5             : IN    std_ulogic := 'U';
        AR6             : IN    std_ulogic := 'U';
        AR7             : IN    std_ulogic := 'U';
        AR8             : IN    std_ulogic := 'U';
        AR9             : IN    std_ulogic := 'U';
        AR10            : IN    std_ulogic := 'U';
        AR11            : IN    std_ulogic := 'U';
        AR12            : IN    std_ulogic := 'U';
        AR13            : IN    std_ulogic := 'U';
        AR14            : IN    std_ulogic := 'U';
        AL0             : IN    std_ulogic := 'U';
        AL1             : IN    std_ulogic := 'U';
        AL2             : IN    std_ulogic := 'U';
        AL3             : IN    std_ulogic := 'U';
        AL4             : IN    std_ulogic := 'U';
        AL5             : IN    std_ulogic := 'U';
        AL6             : IN    std_ulogic := 'U';
        AL7             : IN    std_ulogic := 'U';
        AL8             : IN    std_ulogic := 'U';
        AL9             : IN    std_ulogic := 'U';
        AL10            : IN    std_ulogic := 'U';
        AL11            : IN    std_ulogic := 'U';
        AL12            : IN    std_ulogic := 'U';
        AL13            : IN    std_ulogic := 'U';
        AL14            : IN    std_ulogic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of idt709079 : ENTITY IS TRUE;
END idt709079;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of idt709079 IS
    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    CONSTANT partID         : STRING := "IDT709079";
    CONSTANT MaxData        : NATURAL := 255;
    CONSTANT TotalLOC       : NATURAL := 32767;
    CONSTANT HiAbit         : NATURAL := 14;
    CONSTANT HiDbit         : NATURAL := 7;
    CONSTANT DataWidth      : NATURAL := 8;

    SIGNAL RWR_ipd             : std_ulogic := 'U';
    SIGNAL RWL_ipd             : std_ulogic := 'U';
    SIGNAL CE1R_ipd            : std_ulogic := 'U';
    SIGNAL CE1L_ipd            : std_ulogic := 'U';
    SIGNAL PIPER_ipd           : std_ulogic := 'U';
    SIGNAL CLKR_ipd            : std_ulogic := 'U';
    SIGNAL CLKL_ipd            : std_ulogic := 'U';
    SIGNAL CNTENRNeg_ipd       : std_ulogic := 'U';
    SIGNAL CNTENLNeg_ipd       : std_ulogic := 'U';
    SIGNAL CNTRSTRNeg_ipd      : std_ulogic := 'U';
    SIGNAL CNTRSTLNeg_ipd      : std_ulogic := 'U';
    SIGNAL ADSRNeg_ipd         : std_ulogic := 'U';
    SIGNAL ADSLNeg_ipd         : std_ulogic := 'U';
    SIGNAL CE0RNeg_ipd         : std_ulogic := 'U';
    SIGNAL CE0LNeg_ipd         : std_ulogic := 'U';
    SIGNAL OERNeg_ipd          : std_ulogic := 'U';
    SIGNAL OELNeg_ipd          : std_ulogic := 'U';
    SIGNAL IOR7_ipd            : std_ulogic := 'U';
    SIGNAL IOR6_ipd            : std_ulogic := 'U';
    SIGNAL IOR5_ipd            : std_ulogic := 'U';
    SIGNAL IOR4_ipd            : std_ulogic := 'U';
    SIGNAL IOR3_ipd            : std_ulogic := 'U';
    SIGNAL IOR2_ipd            : std_ulogic := 'U';
    SIGNAL IOR1_ipd            : std_ulogic := 'U';
    SIGNAL IOR0_ipd            : std_ulogic := 'U';
    SIGNAL IOL7_ipd            : std_ulogic := 'U';
    SIGNAL IOL6_ipd            : std_ulogic := 'U';
    SIGNAL IOL5_ipd            : std_ulogic := 'U';
    SIGNAL IOL4_ipd            : std_ulogic := 'U';
    SIGNAL IOL3_ipd            : std_ulogic := 'U';
    SIGNAL IOL2_ipd            : std_ulogic := 'U';
    SIGNAL IOL1_ipd            : std_ulogic := 'U';
    SIGNAL IOL0_ipd            : std_ulogic := 'U';
    SIGNAL AR0_ipd             : std_ulogic := 'U';
    SIGNAL AR1_ipd             : std_ulogic := 'U';
    SIGNAL AR2_ipd             : std_ulogic := 'U';
    SIGNAL AR3_ipd             : std_ulogic := 'U';
    SIGNAL AR4_ipd             : std_ulogic := 'U';
    SIGNAL AR5_ipd             : std_ulogic := 'U';
    SIGNAL AR6_ipd             : std_ulogic := 'U';
    SIGNAL AR7_ipd             : std_ulogic := 'U';
    SIGNAL AR8_ipd             : std_ulogic := 'U';
    SIGNAL AR9_ipd             : std_ulogic := 'U';
    SIGNAL AR10_ipd            : std_ulogic := 'U';
    SIGNAL AR11_ipd            : std_ulogic := 'U';