📄 cy7c1353b.ftm

📁 vhdl cod for ram.For sp3e
💻 FTM
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<!DOCTYPE FTML SYSTEM "ftml.dtd"><FTML><HEAD><TITLE>FMF Timing for CY7C1353B Parts</TITLE><REVISION.HISTORY>version: |  author:  | mod date: | changes made:  V1.0      B.BIZIC    01 JUN 13  Initial release</REVISION.HISTORY></HEAD><BODY><TIMESCALE>1ns</TIMESCALE><MODEL>CY7C1353B<FMFTIME>CY7C1353B-117AC<SOURCE>Cypress Semiconductor Data Sheet April 4, 2000</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, CL=5pF, Ta=0 to 70 Celsius</COMMENT><COMMENT> Typical values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQ0 (2.5:3.5:7.5) (2.5:3.5:4.2) (1.5:2.85:4.2) (2.5:3.5:4.2) (1.5:2.85:4.2) (2.5:3.5:4.2))     (IOPATH OENeg DQ0 () () (1.5:3.5:4.2) (0.0:2.1:4.2) (1.5:3.5:4.2) (0.0:2.1:4.2))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (8.5))    (WIDTH  (posedge CLK) (1.9))    (WIDTH  (negedge CLK) (1.9))    (SETUP A0 CLK (2.0))    (SETUP CLKENNeg CLK (2.0))    (SETUP DQA0 CLK (2.0))    (SETUP R CLK (2.0))    (SETUP ADV CLK (2.0))    (SETUP CE2 CLK (2.0))    (SETUP BWANeg CLK (2.0))    (HOLD A0 CLK (0.5))    (HOLD CLKENNeg CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD R CLK (0.5))    (HOLD ADV CLK (0.5))    (HOLD CE2 CLK (0.5))    (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>CY7C1353B-100AC<SOURCE>Cypress Semiconductor Data Sheet April 4, 2000</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, CL=5pF, Ta=0 to 70 Celsius</COMMENT><COMMENT> Typical values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQ0 (2.5:4.0:8.5) (2.5:4.0:5.0) (1.5:3.25:5.0) (2.5:4.0:5.0) (1.5:3.25:5.0) (2.5:4.0:5.0))     (IOPATH OENeg DQ0 () () (2.5:4.0:5.0) (1.0:2.5:5.0) (2.5:4.0:5.0) (1.0:2.5:5.0))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (10))    (WIDTH  (posedge CLK) (1.9))    (WIDTH  (negedge CLK) (1.9))    (SETUP A0 CLK (2.0))    (SETUP CLKENNeg CLK (2.0))    (SETUP DQA0 CLK (2.0))    (SETUP R CLK (2.0))    (SETUP ADV CLK (2.0))    (SETUP CE2 CLK (2.0))    (SETUP BWANeg CLK (2.0))    (HOLD A0 CLK (0.5))    (HOLD CLKENNeg CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD R CLK (0.5))    (HOLD ADV CLK (0.5))    (HOLD CE2 CLK (0.5))    (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>CY7C1353B-66AC<SOURCE>Cypress Semiconductor Data Sheet April 4, 2000</SOURCE>CY7C1353B-66BGC<SOURCE>Cypress Semiconductor Data Sheet April 4, 2000</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, CL=5pF, Ta=0 to 70 Celsius</COMMENT><COMMENT> Typical values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQ0 (2.5:5.0:11.0) (2.5:5.0:7.0) (1.5:3.25:5.0) (2.5:5.0:7.0) (1.5:3.25:5.0) (2.5:5.0:7.0))     (IOPATH OENeg DQ0 () () (2.5:4.0:6.0) (1.0:5.0:7.0) (2.5:4.0:6.0) (1.0:5.0:7.0))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (15.0))    (WIDTH  (posedge CLK) (5.0))    (WIDTH  (negedge CLK) (5.0))    (SETUP A0 CLK (2.0))    (SETUP CLKENNeg CLK (2.0))    (SETUP DQA0 CLK (2.0))    (SETUP R CLK (2.0))    (SETUP ADV CLK (2.0))    (SETUP CE2 CLK (2.0))    (SETUP BWANeg CLK (2.0))    (HOLD A0 CLK (0.5))    (HOLD CLKENNeg CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD R CLK (0.5))    (HOLD ADV CLK (0.5))    (HOLD CE2 CLK (0.5))    (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>CY7C1353B-50AC<SOURCE>Cypress Semiconductor Data Sheet April 4, 2000</SOURCE>CY7C1353B-50BGC<SOURCE>Cypress Semiconductor Data Sheet April 4, 2000</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, CL=5pF, Ta=0 to 70 Celsius</COMMENT><COMMENT> Typical values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQ0 (2.5:8.0:12.0) (2.5:8.0:10.0) (1.5:3.25:5.0) (2.5:4.0:10.0) (1.5:3.25:5.0) (2.5:4.0:10.0))     (IOPATH OENeg DQ0 () () (2.5:4.0:6.0) (1.0:5.0:10.0) (2.5:4.0:6.0) (1.0:5.0:10.0))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (20))    (WIDTH  (posedge CLK) (6.0))    (WIDTH  (negedge CLK) (6.0))    (SETUP A0 CLK (2.0))    (SETUP CLKENNeg CLK (2.0))    (SETUP DQA0 CLK (2.0))    (SETUP R CLK (2.0))    (SETUP ADV CLK (2.0))    (SETUP CE2 CLK (2.0))    (SETUP BWANeg CLK (2.0))    (HOLD A0 CLK (1.0))    (HOLD CLKENNeg CLK (1.0))    (HOLD DQA0 CLK (1.0))    (HOLD R CLK (1.0))    (HOLD ADV CLK (1.0))    (HOLD CE2 CLK (1.0))    (HOLD BWANeg CLK (1.0)) )</TIMING></FMFTIME><FMFTIME>CY7C1353B-40AC<SOURCE>Cypress Semiconductor Data Sheet April 4, 2000</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, CL=5pF, Ta=0 to 70 Celsius</COMMENT><COMMENT> Typical values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQ0 (2.5:8.0:14.0) (2.5:8.0:10.0) (1.5:3.25:5.0) (2.5:4.0:10.0) (1.5:3.25:5.0) (2.5:4.0:10.0))     (IOPATH OENeg DQ0 () () (2.5:4.0:6.0) (1.0:5.0:10.0) (2.5:4.0:6.0) (1.0:5.0:10.0))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (25))    (WIDTH  (posedge CLK) (7.0))    (WIDTH  (negedge CLK) (7.0))    (SETUP A0 CLK (2.5))    (SETUP CLKENNeg CLK (2.5))    (SETUP DQA0 CLK (2.5))    (SETUP R CLK (2.5))    (SETUP ADV CLK (2.5))    (SETUP CE2 CLK (2.5))    (SETUP BWANeg CLK (2.5))    (HOLD A0 CLK (1.0))    (HOLD CLKENNeg CLK (1.0))    (HOLD DQA0 CLK (1.0))    (HOLD R CLK (1.0))    (HOLD ADV CLK (1.0))    (HOLD CE2 CLK (1.0))    (HOLD BWANeg CLK (1.0)) )</TIMING></FMFTIME><FMFTIME>MCM63Z819TQ10<SOURCE>Motorola Semiconductor MCM63Z737/D 1/14/00</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, CL=5pF, Ta=0 to 70 Celsius</COMMENT><COMMENT> Typical values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQ0 (1.5:7:10) (1.5:7:10) (1.5:3.0:4.5) (1.5:7:10) (1.5:3.0:4.5) (1.5:7:10))     (IOPATH OENeg DQ0 () () (1.5:3.0:4.5) (0.0:2.25:5) (1.5:3.0:4.5) (0.0:2.25:5))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (12))    (WIDTH  (posedge CLK) (4.8))    (WIDTH  (negedge CLK) (4.8))    (SETUP A0 CLK (2.5))    (SETUP ADV CLK (2.5))    (SETUP DQA0 CLK (2.0))    (SETUP R CLK (2.5))    (SETUP CE2 CLK (2.5))    (SETUP CLKENNeg CLK (2.5))    (SETUP BWANeg CLK (2.5))    (HOLD A0 CLK (0.5))    (HOLD ADV CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD R CLK (0.5))    (HOLD CE2 CLK (0.5))    (HOLD CLKENNeg CLK (0.5))    (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>MCM63Z819TQ11<SOURCE>Motorola Semiconductor MCM63Z737/D 1/14/00</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, CL=5pF, Ta=0 to 70 Celsius</COMMENT><COMMENT> Typical values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQ0 (1.5:7.5:11) (1.5:7.5:11) (1.5:3.0:4.5) (1.5:7.5:11) (1.5:3.0:4.5) (1.5:7.5:11)     (IOPATH OENeg DQ0 () () (1.5:3.0:4.5) (0.0:2.25:6.0) (1.5:3.0:4.5) (0.0:2.25:6.0))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (15))    (WIDTH  (posedge CLK) (6.0))    (WIDTH  (negedge CLK) (6.0))    (SETUP A0 CLK (2.5))    (SETUP ADV CLK (2.5))    (SETUP DQA0 CLK (2.0))    (SETUP R CLK (2.5))    (SETUP CE2 CLK (2.5))    (SETUP CLKENNeg CLK (2.5))    (SETUP BWANeg CLK (2.5))    (HOLD A0 CLK (0.5))    (HOLD ADV CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD R CLK (0.5))    (HOLD CE2 CLK (0.5))    (HOLD CLKENNeg CLK (0.5))    (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>MCM63Z819TQ15<SOURCE>Motorola Semiconductor MCM63Z737/D 1/14/00</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, CL=5pF, Ta=0 to 70 Celsius</COMMENT><COMMENT> Typical values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQ0 (1.5:10:15) (1.5:10:15) (1.5:3.25:5.0) (1.5:10:15) (1.5:3.25:5.0) (1.5:10:15)     (IOPATH OENeg DQ0 () () (1.5:3.25:5.0) (0.0:2.5:7.0) (1.5:3.25:5.0) (0.0:2.5:7.0))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (20.0))    (WIDTH  (posedge CLK) (8.0))    (WIDTH  (negedge CLK) (8.0))    (SETUP A0 CLK (2.5))    (SETUP ADV CLK (2.5))    (SETUP DQA0 CLK (2.0))    (SETUP R CLK (2.5))    (SETUP CE2 CLK (2.5))    (SETUP CLKENNeg CLK (2.5))    (SETUP BWANeg CLK (2.5))    (HOLD A0 CLK (0.5))    (HOLD ADV CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD R CLK (0.5))    (HOLD CE2 CLK (0.5))    (HOLD CLKENNeg CLK (0.5))    (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>MT55L256L18F1B-10<SOURCE>Micron Technology, Inc., MT55L256L18F1_C.p65
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