📄 idt71v546.ftm

📁 vhdl cod for ram.For sp3e
💻 FTM
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<!DOCTYPE FTML SYSTEM "ftml.dtd"><FTML><HEAD><TITLE>FMF Timing for IDT71V546 Parts</TITLE><REVISION.HISTORY>version: |  author:  | mod date: | changes made:  V1.0     R. Munden   98 DEC 15   Initial release  V1.1     R. Munden   99 JAN 28   Added 4 more part numbers  V2.0     R. Munden   00 JAN 29   Renamed ports to match 2.0 model                                   Updated IDT specs</REVISION.HISTORY></HEAD><BODY><TIMESCALE>1ns</TIMESCALE><MODEL>IDT71V546<FMFTIME>CY7C1350-143A<SOURCE>Cypress Semiconductor Preliminary Datasheet Rev. April 1998</SOURCE><COMMENT> The values listed are for VCC=3.3V, Ta=0 to +70 Celsius</COMMENT><COMMENT>missing parameters were derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQA0 (2.0:3.1:4.0) (2.0:3.1:4.0) (1.5:2.6:3.5) (2.0:3.1:4.0) (1.5:2.6:3.5) (2.0:3.1:4.0))     (IOPATH OENeg DQA0 () () (0.0:2.6:4.0) (0.0:3.6:4.0) (0.0:2.6:4.0) (0.0:3.6:4.0))  ))  (TIMINGCHECK    (WIDTH  (posedge CLK) (2.0))    (WIDTH  (negedge CLK) (2.0))    (PERIOD (posedge CLK) (7.0))    (SETUP CLKENNeg CLK (2.0))    (SETUP A0 CLK (2.0))    (SETUP DQA0 CLK (1.7))    (SETUP R CLK (2.0))    (SETUP ADV CLK (2.0))    (SETUP CE2 CLK (2.0))    (SETUP BWANeg CLK (2.0))    (HOLD CLKENNeg CLK (0.5))    (HOLD A0 CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD R CLK (0.5))    (HOLD ADV CLK (0.5))    (HOLD CE2 CLK (0.5))    (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>CY7C1350-133A<SOURCE>Cypress Semiconductor Preliminary Datasheet Rev. April 1998</SOURCE><COMMENT> The values listed are for VCC=3.3V, Ta=0 to +70 Celsius</COMMENT><COMMENT>missing parameters were derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQA0 (2.0:3.2:4.2) (2.0:3.2:4.2) (1.5:2.6:3.5) (2.0:3.2:4.2) (1.5:2.6:3.5) (2.0:3.2:4.2))     (IOPATH OENeg DQA0 () () (0.0:2.7:4.2) (0.0:3.7:4.2) (0.0:2.7:4.2) (0.0:3.7:4.2))  ))  (TIMINGCHECK    (WIDTH  (posedge CLK) (3.0))    (WIDTH  (negedge CLK) (3.0))    (PERIOD (posedge CLK) (7.5))    (SETUP CLKENNeg CLK (2.0))    (SETUP A0 CLK (2.0))    (SETUP DQA0 CLK (1.7))    (SETUP R CLK (2.0))    (SETUP ADV CLK (2.0))    (SETUP CE2 CLK (2.0))    (SETUP BWANeg CLK (2.0))    (HOLD CLKENNeg CLK (0.5))    (HOLD A0 CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD R CLK (0.5))    (HOLD ADV CLK (0.5))    (HOLD CE2 CLK (0.5))    (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>CY7C1350-100A<SOURCE>Cypress Semiconductor Preliminary Datasheet Rev. April 1998</SOURCE><COMMENT> The values listed are for VCC=3.3V, Ta=0 to +70 Celsius</COMMENT><COMMENT>missing parameters were derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQA0 (2.0:4.0:5.0) (2.0:4.0:5.0) (1.5:2.6:3.5) (2.0:4.0:5.0) (1.5:2.6:3.5) (2.0:4.0:5.0))     (IOPATH OENeg DQA0 () () (0.0:3.2:5.0) (0.0:4.2:5.0) (0.0:3.2:5.0) (0.0:4.2:5.0))  ))  (TIMINGCHECK    (WIDTH  (posedge CLK) (4.0))    (WIDTH  (negedge CLK) (4.0))    (PERIOD (posedge CLK) (10.0))    (SETUP CLKENNeg CLK (2.2))    (SETUP A0 CLK (2.2))    (SETUP DQA0 CLK (2.0))    (SETUP R CLK (2.2))    (SETUP ADV CLK (2.2))    (SETUP CE2 CLK (2.2))    (SETUP BWANeg CLK (2.2))    (HOLD CLKENNeg CLK (0.5))    (HOLD A0 CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD R CLK (0.5))    (HOLD ADV CLK (0.5))    (HOLD CE2 CLK (0.5))    (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>CY7C1350-80A<SOURCE>Cypress Semiconductor Preliminary Datasheet Rev. April 1998</SOURCE><COMMENT> The values listed are for VCC=3.3V, Ta=0 to +70 Celsius</COMMENT><COMMENT>missing parameters were derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQA0 (2.0:5.0:7.0) (2.0:5.0:7.0) (1.5:3.0:5.0) (2.0:5.0:7.0) (1.5:3.0:5.0) (2.0:5.0:7.0))     (IOPATH OENeg DQA0 () () (0.0:3.5:7.0) (0.0:4.5:7.0) (0.0:3.5:7.0) (0.0:4.5:7.0))  ))  (TIMINGCHECK    (WIDTH  (posedge CLK) (4.0))    (WIDTH  (negedge CLK) (4.0))    (PERIOD (posedge CLK) (12.5))    (SETUP CLKENNeg CLK (2.5))    (SETUP A0 CLK (2.5))    (SETUP DQA0 CLK (2.5))    (SETUP R CLK (2.5))    (SETUP ADV CLK (2.5))    (SETUP CE2 CLK (2.5))    (SETUP BWANeg CLK (2.5))    (HOLD CLKENNeg CLK (1.0))    (HOLD A0 CLK (1.0))    (HOLD DQA0 CLK (1.0))    (HOLD R CLK (1.0))    (HOLD ADV CLK (1.0))    (HOLD CE2 CLK (1.0))    (HOLD BWANeg CLK (1.0)) )</TIMING></FMFTIME><FMFTIME>IDT71V546S133PF<SOURCE>IDT Datasheet DSC-3821/03 Rev. December 1999</SOURCE><COMMENT> The values listed are for VCC=3.3V, Ta=0 to +70 Celsius</COMMENT><COMMENT>For each parameter only min or max values were supplied by vendor - all others were derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQA0 (1.3:3.3:4.2) (1.3:3.3:4.2) (1.5:2.6:3.5) (1.5:3.4:4.5) (1.5:2.6:3.5) (1.5:3.4:4.5))     (IOPATH OENeg DQA0 () () (0.0:2.6:3.5) (0.0:3.6:4.2) (0.0:2.6:3.5) (0.0:3.6:4.2))  ))  (TIMINGCHECK    (WIDTH  (posedge CLK) (2.5))    (WIDTH  (negedge CLK) (2.5))    (PERIOD (posedge CLK) (7.5))    (SETUP CLKENNeg CLK (2.0))    (SETUP A0 CLK (2.0))    (SETUP DQA0 CLK (1.7))    (SETUP R CLK (2.0))    (SETUP ADV CLK (2.0))    (SETUP CE2 CLK (2.0))    (SETUP BWANeg CLK (2.0))    (HOLD CLKENNeg CLK (0.5))    (HOLD A0 CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD R CLK (0.5))    (HOLD ADV CLK (0.5))    (HOLD CE2 CLK (0.5))    (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>IDT71V546S117PF<SOURCE>IDT Datasheet DSC-3821/03 Rev. December 1999</SOURCE><COMMENT> The values listed are for VCC=3.3V, Ta=0 to +70 Celsius</COMMENT><COMMENT>For each parameter only min or max values were supplied by vendor - all others were derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQA0 (1.5:3.4:4.5) (1.5:3.4:4.5) (1.5:2.6:3.5) (1.5:3.4:4.5) (1.5:2.6:3.5) (1.5:3.4:4.5))     (IOPATH OENeg DQA0 () () (0.0:2.6:3.5) (0.0:3.6:4.5) (0.0:2.6:3.5) (0.0:3.6:4.5))  ))  (TIMINGCHECK    (WIDTH  (posedge CLK) (3.0))    (WIDTH  (negedge CLK) (3.0))    (PERIOD (posedge CLK) (8.5))    (SETUP CLKENNeg CLK (2.0))    (SETUP A0 CLK (2.0))    (SETUP DQA0 CLK (1.7))    (SETUP R CLK (2.0))    (SETUP ADV CLK (2.0))    (SETUP CE2 CLK (2.0))    (SETUP BWANeg CLK (2.0))    (HOLD CLKENNeg CLK (0.5))    (HOLD A0 CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD R CLK (0.5))    (HOLD ADV CLK (0.5))    (HOLD CE2 CLK (0.5))    (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>IDT71V546S100PF<SOURCE>IDT Datasheet DSC-3821/03 Rev. December 1999</SOURCE><COMMENT> The values listed are for VCC=3.3V, Ta=0 to +70 Celsius</COMMENT><COMMENT>For each parameter only min or max values were supplied by vendor - all others were derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQA0 (1.5:3.6:5.0) (1.5:3.6:5.0) (1.5:2.6:3.5) (1.5:3.6:5.0) (1.5:2.6:3.5) (1.5:3.6:5.0))     (IOPATH OENeg DQA0 () () (0.0:2.6:3.5) (0.0:3.6:5.0) (0.0:2.6:3.5) (0.0:3.6:5.0))  ))  (TIMINGCHECK    (WIDTH  (posedge CLK) (3.5))    (WIDTH  (negedge CLK) (3.6))    (PERIOD (posedge CLK) (10))    (SETUP CLKENNeg CLK (2.2))    (SETUP A0 CLK (2.2))    (SETUP DQA0 CLK (2.0))    (SETUP R CLK (2.2))    (SETUP ADV CLK (2.2))    (SETUP CE2 CLK (2.2))    (SETUP BWANeg CLK (2.2))    (HOLD CLKENNeg CLK (0.5))    (HOLD A0 CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD R CLK (0.5))    (HOLD ADV CLK (0.5))    (HOLD CE2 CLK (0.5))    (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>IDT71V546S83PF<SOURCE>IDT Preliminary Datasheet Rev. April 1998</SOURCE><COMMENT> The values listed are for VCC=3.3V, Ta=0 to +70 Celsius</COMMENT><COMMENT>For each parameter only min or max values were supplied by vendor - all others were derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQA0 (1.5:4.0:6.0) (1.5:4.0:6.0) (1.5:2.6:3.5) (1.5:4.0:6.0) (1.5:2.6:3.5) (1.5:4.0:6.0))     (IOPATH OENeg DQA0 () () (0.0:2.6:3.5) (0.0:3.6:6.0) (0.0:2.6:3.5) (0.0:3.6:6.0))  ))  (TIMINGCHECK    (WIDTH  (posedge CLK) (4.0))    (WIDTH  (negedge CLK) (4.0))    (PERIOD (posedge CLK) (12))    (SETUP CLKENNeg CLK (2.5))    (SETUP A0 CLK (2.5))    (SETUP DQA0 CLK (2.5))    (SETUP R CLK (2.5))    (SETUP ADV CLK (2.5))    (SETUP CE2 CLK (2.5))    (SETUP BWANeg CLK (2.5))    (HOLD CLKENNeg CLK (0.5))    (HOLD A0 CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD R CLK (0.5))    (HOLD ADV CLK (0.5))    (HOLD CE2 CLK (0.5))    (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>MCM63Z736TQ100<SOURCE>Motorola Datasheet MCM63X736/D Rev 3 9/28/98</SOURCE><COMMENT> The values listed are for VCC=3.3V, Ta=0 to +70 Celsius</COMMENT><COMMENT>For each parameter only min or max values were supplied by vendor - all others were derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQA0 (1.5:3.6:5.0) (1.5:3.6:5.0) (1.5:2.6:3.5) (1.5:3.6:5.0) (1.5:2.6:3.5) (1.5:3.6:5.0))     (IOPATH OENeg DQA0 () () (0.0:2.6:3.5) (0.0:3.6:5.0) (0.0:2.6:3.5) (0.0:3.6:5.0))  ))  (TIMINGCHECK    (WIDTH  (posedge CLK) (4.0))    (WIDTH  (negedge CLK) (4.0))    (PERIOD (posedge CLK) (10))    (SETUP CLKENNeg CLK (2.2))    (SETUP A0 CLK (2.2))    (SETUP DQA0 CLK (2.0))    (SETUP R CLK (2.2))    (SETUP ADV CLK (2.2))    (SETUP CE2 CLK (2.2))    (SETUP BWANeg CLK (2.2))    (HOLD CLKENNeg CLK (0.5))    (HOLD A0 CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD R CLK (0.5))    (HOLD ADV CLK (0.5))    (HOLD CE2 CLK (0.5))    (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>MCM63Z736TQ133<SOURCE>Motorola Datasheet MCM63X736/D Rev 3 9/28/98</SOURCE><COMMENT> The values listed are for VCC=3.3V, Ta=0 to +70 Celsius</COMMENT><COMMENT>For each parameter only min or max values were supplied by vendor - all others were derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQA0 (1.3:3.3:4.2) (1.3:3.3:4.2) (1.5:2.6:3.5) (1.5:3.4:4.5) (1.5:2.6:3.5) (1.5:3.4:4.5))     (IOPATH OENeg DQA0 () () (0.0:2.6:3.5) (0.0:3.6:4.2) (0.0:2.6:3.5) (0.0:3.6:4.2))  ))  (TIMINGCHECK    (WIDTH  (posedge CLK) (3.0))    (WIDTH  (negedge CLK) (3.0))    (PERIOD (posedge CLK) (7.5))    (SETUP CLKENNeg CLK (2.0))    (SETUP A0 CLK (2.0))    (SETUP DQA0 CLK (1.7))    (SETUP R CLK (2.0))    (SETUP ADV CLK (2.0))    (SETUP CE2 CLK (2.0))    (SETUP BWANeg CLK (2.0))    (HOLD CLKENNeg CLK (0.5))    (HOLD A0 CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD R CLK (0.5))    (HOLD ADV CLK (0.5))    (HOLD CE2 CLK (0.5))    (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>MCM63Z736TQ143<SOURCE>Motorola Datasheet MCM63X736/D Rev 3 9/28/98</SOURCE><COMMENT> The values listed are for VCC=3.3V, Ta=0 to +70 Celsius</COMMENT><COMMENT>For each parameter only min or max values were supplied by vendor - all others were derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQA0 (1.3:3.1:4.0) (1.3:3.1:4.0) (1.5:2.6:3.5) (1.5:3.1:4.0) (1.5:2.6:3.5) (1.5:3.1:4.0))     (IOPATH OENeg DQA0 () () (0.0:2.6:3.5) (0.0:3.6:4.2) (0.0:2.6:3.5) (0.0:3.6:4.2))  ))  (TIMINGCHECK    (WIDTH  (posedge CLK) (2.8))    (WIDTH  (negedge CLK) (2.8))    (PERIOD (posedge CLK) (7.0))    (SETUP CLKENNeg CLK (2.0))    (SETUP A0 CLK (2.0))    (SETUP DQA0 CLK (1.7))    (SETUP R CLK (2.0))    (SETUP ADV CLK (2.0))    (SETUP CE2 CLK (2.0))    (SETUP BWANeg CLK (2.0))    (HOLD CLKENNeg CLK (0.5))    (HOLD A0 CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD R CLK (0.5))    (HOLD ADV CLK (0.5))    (HOLD CE2 CLK (0.5))    (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME></BODY></FTML>
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