📄 cy7c1480.ftm

📁 vhdl cod for ram.For sp3e
💻 FTM
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 <!DOCTYPE FTML SYSTEM "ftml.dtd"><FTML><HEAD><TITLE>FMF Timing for cy7c1480v33 Parts</TITLE><BODY><REVISION.HISTORY>version: |  author:         | mod date: | changes made:  V1.0    V.Ljubisavljevic    04 Sep 23   Initial release</REVISION.HISTORY><TIMESCALE>1ns</TIMESCALE><MODEL>cy7c1480v33<FMFTIME>CY7C1480V33-167AC<SOURCE>Cypress 38-05283 Rev. *A Revised Jan 18,2003</SOURCE>CY7C1480V33-167BGC<SOURCE>Cypress 38-05283 Rev. *A Revised Jan 18,2003</SOURCE>CY7C1480V33-167BZC<SOURCE>Cypress 38-05283 Rev. *A Revised Jan 18,2003</SOURCE><COMMENT>The values listed are for Vdd=3.135V to 3.465V, CL=TBD uF, Ta=0 to +70 Celsius</COMMENT><COMMENT>Values not supplied by vendor are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH CLK DQA0 (3.4:3.4:3.4) (3.4:3.4:3.4) (3.4:3.4:3.4) (1.5:1.5:1.5) (3.4:3.4:3.4) (1.5:1.5:1.5))    (IOPATH OENeg DQA0 ()()(3.4:3.4:3.4) (3.4:3.4:3.4)(3.4:3.4:3.4)(3.4:3.4:3.4))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (6.0))    (WIDTH (posedge CLK)(2.4))    (WIDTH (negedge CLK)(2.4))    (SETUP A0 CLK (1.5))    (SETUP DQA0 CLK (1.5))    (SETUP ADVNeg CLK (1.5))    (SETUP ADSCNeg CLK (1.5))    (SETUP BWANeg CLK (1.5))    (SETUP CE2 CLK (1.5))    (HOLD A0 CLK (.5))    (HOLD DQA0 CLK (.5))    (HOLD ADSCNeg CLK (.5))    (HOLD BWANeg CLK (.5))    (HOLD ADVNeg CLK (.5))    (HOLD CE2 CLK (.5))    (HOLD ADSCNeg ZZ (12.0))  )</TIMING></FMFTIME><FMFTIME>CY7C1480V33-200AC<SOURCE>Cypress 38-05283 Rev. *A Revised Jan 18,2003</SOURCE>CY7C1480V33-200BGC<SOURCE>Cypress 38-05283 Rev. *A Revised Jan 18,2003</SOURCE>CY7C1480V33-200BZC<SOURCE>Cypress 38-05283 Rev. *A Revised Jan 18,2003</SOURCE><COMMENT>The values listed are for Vdd=3.135V to 3.465V, CL=TBD uF, Ta=0 to +70 Celsius</COMMENT><COMMENT>Values not supplied by vendor are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH CLK DQA0 (3:3:3) (3:3:3) (3:3:3) (1.3:1.3:1.3) (3:3:3) (1.3:1.3:1.3))    (IOPATH OENeg DQA0 ()()(3:3:3) (3:3:3)(3:3:3)(3:3:3))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (5))    (WIDTH (posedge CLK)(2))    (WIDTH (negedge CLK)(2))    (SETUP A0 CLK (1.4))    (SETUP DQA0 CLK (1.4))    (SETUP ADVNeg CLK (1.4))    (SETUP ADSCNeg CLK (1.4))    (SETUP BWANeg CLK (1.4))    (SETUP CE2 CLK (1.4))    (HOLD A0 CLK (.4))    (HOLD DQA0 CLK (.4))    (HOLD ADSCNeg CLK (.4))    (HOLD BWANeg CLK (.4))    (HOLD ADVNeg CLK (.4))    (HOLD CE2 CLK (.4))    (HOLD ADSCNeg ZZ (10))  )</TIMING></FMFTIME><FMFTIME>CY7C1480V33-250AC<SOURCE>Cypress 38-05283 Rev. *A Revised Jan 18,2003</SOURCE>CY7C1480V33-250BGC<SOURCE>Cypress 38-05283 Rev. *A Revised Jan 18,2003</SOURCE>CY7C1480V33-250BZC<SOURCE>Cypress 38-05283 Rev. *A Revised Jan 18,2003</SOURCE><COMMENT>The values listed are for Vdd=3.135V to 3.465V, CL=TBD uF, Ta=0 to +70 Celsius</COMMENT><COMMENT>Values not supplied by vendor are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH CLK DQA0 (2.6:2.6:2.6) (2.6:2.6:2.6) (2.6:2.6:2.6) (1:1:1) (2.6:2.6:2.6) (1:1:1))    (IOPATH OENeg DQA0 ()()(2.6:2.6:2.6) (2.6:2.6:2.6)(2.6:2.6:2.6)(2.6:2.6:2.6))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (4))    (WIDTH (posedge CLK)(1.7))    (WIDTH (negedge CLK)(1.7))    (SETUP A0 CLK (1.2))    (SETUP DQA0 CLK (1.2))    (SETUP ADVNeg CLK (1.2))    (SETUP ADSCNeg CLK (1.2))    (SETUP BWANeg CLK (1.2))    (SETUP CE2 CLK (1.2))    (HOLD A0 CLK (.3))    (HOLD DQA0 CLK (.3))    (HOLD ADSCNeg CLK (.3))    (HOLD BWANeg CLK (.3))    (HOLD ADVNeg CLK (.3))    (HOLD CE2 CLK (.3))    (HOLD ADSCNeg ZZ (8))  )</TIMING></FMFTIME></BODY></FTML>
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