cy7c1360.vhd

vhdl cod for ram.For sp3e

                            CE3NegIn, ZZIn)

            -- Type definition for commands
            TYPE command_type IS (ds,
                                  SPwr_burst,
                                  SPwr_susp,
                                  SCwr,
                                  begin_rw,
                                  SCrd,
                                  read_burst,
                                  read_susp
                                 );

            -- Timing Check Variables

            VARIABLE Tviol_AddressIn_CLK : X01 := '0';
            VARIABLE TD_AddressIn_CLK    : VitalTimingDataType;

            VARIABLE Tviol_DatDIn_CLK    : X01 := '0';
            VARIABLE TD_DatDIn_CLK       : VitalTimingDataType;

            VARIABLE Tviol_DatCIn_CLK    : X01 := '0';
            VARIABLE TD_DatCIn_CLK       : VitalTimingDataType;

            VARIABLE Tviol_DatBIn_CLK    : X01 := '0';
            VARIABLE TD_DatBIn_CLK       : VitalTimingDataType;

            VARIABLE Tviol_DatAIn_CLK    : X01 := '0';
            VARIABLE TD_DatAIn_CLK       : VitalTimingDataType;

            VARIABLE Tviol_BWDN_CLK      : X01 := '0';
            VARIABLE TD_BWDN_CLK         : VitalTimingDataType;

            VARIABLE Tviol_BWCN_CLK      : X01 := '0';
            VARIABLE TD_BWCN_CLK         : VitalTimingDataType;

            VARIABLE Tviol_BWBN_CLK      : X01 := '0';
            VARIABLE TD_BWBN_CLK         : VitalTimingDataType;

            VARIABLE Tviol_BWAN_CLK      : X01 := '0';
            VARIABLE TD_BWAN_CLK         : VitalTimingDataType;

            VARIABLE Tviol_BWEN_CLK      : X01 := '0';
            VARIABLE TD_BWEN_CLK         : VitalTimingDataType;

            VARIABLE Tviol_GWN_CLK       : X01 := '0';
            VARIABLE TD_GWN_CLK          : VitalTimingDataType;

            VARIABLE Tviol_ADVNIn_CLK    : X01 := '0';
            VARIABLE TD_ADVNIn_CLK       : VitalTimingDataType;

            VARIABLE Tviol_ADSCNIn_CLK   : X01 := '0';
            VARIABLE TD_ADSCNIn_CLK      : VitalTimingDataType;

            VARIABLE Tviol_ADSPNIn_CLK   : X01 := '0';
            VARIABLE TD_ADSPNIn_CLK      : VitalTimingDataType;

            VARIABLE Tviol_CE1NegIn_CLK  : X01 := '0';
            VARIABLE TD_CE1NegIn_CLK     : VitalTimingDataType;

            VARIABLE Tviol_CE3NegIn_CLK  : X01 := '0';
            VARIABLE TD_CE3NegIn_CLK     : VitalTimingDataType;

            VARIABLE Tviol_CE2In_CLK     : X01 := '0';
            VARIABLE TD_CE2In_CLK        : VitalTimingDataType;

            VARIABLE Pviol_CLK    : X01 := '0';
            VARIABLE PD_CLK       : VitalPeriodDataType := VitalPeriodDataInit;

            VARIABLE MemAddr    : natural RANGE 0 TO MemSize;
            VARIABLE startaddr  : natural RANGE 0 TO MemSize;

            VARIABLE Burst_Cnt  : natural RANGE 0 TO 4 := 0;
            VARIABLE memstart   : natural RANGE 0 TO 3 := 0;
            VARIABLE offset     : integer RANGE -3 TO 3 := 0;

            VARIABLE command    : command_type;
            VARIABLE R          : std_logic;

            VARIABLE zz_reset   : boolean := TRUE;
            VARIABLE zz_start   : boolean := FALSE;
            VARIABLE zz_stop    : boolean := FALSE;
            VARIABLE zz_false   : boolean := FALSE;
            VARIABLE count : natural RANGE 0 TO 2;

            -- Functionality Results Variables
            VARIABLE Violation  : X01 := '0';

            VARIABLE OBuf1      : std_logic_vector(35 DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE OBuf2      : std_logic_vector(35 DOWNTO 0)
                                   := (OTHERS => 'Z');

            PROCEDURE Mem_read IS
            BEGIN
                IF MemDataA(MemAddr) = -2 THEN
                    OBuf1(8 DOWNTO 0) := (OTHERS => 'U');
                ELSIF MemDataA(MemAddr) = -1 THEN
                    OBuf1(8 DOWNTO 0) := (OTHERS => 'X');
                ELSE
                    OBuf1(8 DOWNTO 0) := to_slv(MemDataA(MemAddr),9);
                END IF;
                IF MemDataB(MemAddr) = -2 THEN
                    OBuf1(17 DOWNTO 9) := (OTHERS => 'U');
                ELSIF MemDataB(MemAddr) = -1 THEN
                    OBuf1(17 DOWNTO 9) := (OTHERS => 'X');
                ELSE
                    OBuf1(17 DOWNTO 9) := to_slv(MemDataB(MemAddr),9);
                END IF;
                IF MemDataC(MemAddr) = -2 THEN
                    OBuf1(26 DOWNTO 18) := (OTHERS => 'U');
                ELSIF MemDataC(MemAddr) = -1 THEN
                    OBuf1(26 DOWNTO 18) := (OTHERS => 'X');
                ELSE
                    OBuf1(26 DOWNTO 18) := to_slv(MemDataC(MemAddr),9);
                END IF;
                IF MemDataD(MemAddr) = -2 THEN
                    OBuf1(35 DOWNTO 27) := (OTHERS => 'U');
                ELSIF MemDataD(MemAddr) = -1 THEN
                    OBuf1(35 DOWNTO 27) := (OTHERS => 'X');
                ELSE
                    OBuf1(35 DOWNTO 27) := to_slv(MemDataD(MemAddr),9);
                END IF;
            END Mem_read;

            PROCEDURE Mem_write IS
            BEGIN
                IF GWNIn = '0' THEN
                    MemDataA(MemAddr) := -1;
                    MemDataB(MemAddr) := -1;
                    MemDataC(MemAddr) := -1;
                    MemDataD(MemAddr) := -1;
                    IF Violation /= 'X' THEN
                        MemDataA(MemAddr) := to_nat(DatAIn);
                        MemDataB(MemAddr) := to_nat(DatBIn);
                        MemDataC(MemAddr) := to_nat(DatCIn);
                        MemDataD(MemAddr) := to_nat(DatDIn);
                    END IF;
                ELSE
                    IF (BWANIn = '0') THEN
                        MemDataA(MemAddr) := -1;
                        IF Violation /= 'X' THEN
                            MemDataA(MemAddr) := to_nat(DatAIn);
                        END IF;
                    END IF;
                    IF (BWBNIn = '0') THEN
                        MemDataB(MemAddr) := -1;
                        IF Violation /= 'X' THEN
                            MemDataB(MemAddr) := to_nat(DatBIn);
                        END IF;
                    END IF;
                    IF (BWCNIn = '0') THEN
                        MemDataC(MemAddr) := -1;
                        IF Violation /= 'X' THEN
                            MemDataC(MemAddr) := to_nat(DatCIn);
                        END IF;
                    END IF;
                    IF (BWDNIn = '0') THEN
                        MemDataD(MemAddr) := -1;
                        IF Violation /= 'X' THEN
                            MemDataD(MemAddr) := to_nat(DatDIn);
                        END IF;
                    END IF;
                END IF;
            END Mem_write;

        BEGIN

            --------------------------------------------------------------------
            -- Timing Check Section
            --------------------------------------------------------------------
            IF (TimingChecksOn) THEN

                VitalSetupHoldCheck (
                    TestSignal      => AddressIn,
                    TestSignalName  => "Address",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_A0_CLK,
                    SetupLow        => tsetup_A0_CLK,
                    HoldHigh        => thold_A0_CLK,
                    HoldLow         => thold_A0_CLK,
                    CheckEnabled    => (ZZIn = '0'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_AddressIn_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_AddressIn_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => DatDIn,
                    TestSignalName  => "DatD",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_DQA0_CLK,
                    SetupLow        => tsetup_DQA0_CLK,
                    HoldHigh        => thold_DQA0_CLK,
                    HoldLow         => thold_DQA0_CLK,
                    CheckEnabled    => (ZZIn = '0' AND
                                        DatDIn /= D_zd(35 DOWNTO 27)),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_DatDIn_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_DatDIn_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => DatCIn,
                    TestSignalName  => "DatC",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_DQA0_CLK,
                    SetupLow        => tsetup_DQA0_CLK,
                    HoldHigh        => thold_DQA0_CLK,
                    HoldLow         => thold_DQA0_CLK,
                    CheckEnabled    => (ZZIn = '0' AND
                                        DatCIn /= D_zd(26 DOWNTO 18)),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_DatCIn_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_DatCIn_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => DatBIn,
                    TestSignalName  => "DatB",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_DQA0_CLK,
                    SetupLow        => tsetup_DQA0_CLK,
                    HoldHigh        => thold_DQA0_CLK,
                    HoldLow         => thold_DQA0_CLK,
                    CheckEnabled    => (ZZIn = '0' AND
                                        DatBIn /= D_zd(17 DOWNTO 9)),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_DatBIn_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_DatBIn_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => DatAIn,
                    TestSignalName  => "DatA",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_DQA0_CLK,
                    SetupLow        => tsetup_DQA0_CLK,
                    HoldHigh        => thold_DQA0_CLK,
                    HoldLow         => thold_DQA0_CLK,
                    CheckEnabled    => (ZZIn = '0' AND
                                        DatAIn /= D_zd(8 DOWNTO 0)),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_DatAIn_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_DatAIn_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => GWNIn,
                    TestSignalName  => "GW",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_BWANeg_CLK,
                    SetupLow        => tsetup_BWANeg_CLK,
                    HoldHigh        => thold_BWANeg_CLK,
                    HoldLow         => thold_BWANeg_CLK,
                    CheckEnabled    => (ZZIn ='0'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_GWN_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_GWN_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => BWENIn,
                    TestSignalName  => "BWE",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_BWANeg_CLK,
                    SetupLow        => tsetup_BWANeg_CLK,
                    HoldHigh        => thold_BWANeg_CLK,
                    HoldLow         => thold_BWANeg_CLK,
                    CheckEnabled    => (ZZIn ='0'),
                    RefTransition   => '/',