edj5304ba.vhd

vhdl cod for ram.For sp3e

        SIGNAL CK_COUNT : natural := 0;
        --burst sequences
        TYPE sequence IS ARRAY (0 TO 7) OF integer RANGE -7 TO 7;
        TYPE seqtab   IS ARRAY (0 TO 7) OF sequence;
        CONSTANT seq0 : sequence := (0, 1, 2, 3, 4, 5, 6, 7);
        CONSTANT seq1 : sequence := (0, 1, 2,-1, 4, 5, 6, 3);
        CONSTANT seq2 : sequence := (0, 1,-2,-1, 4, 5, 2, 3);
        CONSTANT seq3 : sequence := (0,-3,-2,-1, 4, 1, 2, 3);
        CONSTANT seq4 : sequence := (0, 1, 2, 3,-4,-3,-2,-1);
        CONSTANT seq5 : sequence := (0, 1, 2,-1,-4,-3,-2,-5);
        CONSTANT seq6 : sequence := (0, 1,-2,-1,-4,-3,-6,-5);
        CONSTANT seq7 : sequence := (0,-3,-2,-1,-4,-7,-6,-5);
        CONSTANT seq  : seqtab   := (seq0, seq1, seq2, seq3, seq4, seq5, seq6,
                                     seq7);
        CONSTANT inl0 : sequence := (0, 1, 2, 3, 4, 5, 6, 7);
        CONSTANT inl1 : sequence := (0,-1, 2, 1, 4, 3, 6, 5);
        CONSTANT inl2 : sequence := (0, 1,-2,-1, 4, 5, 2, 3);
        CONSTANT inl3 : sequence := (0,-1,-2,-3, 4, 3, 2, 1);
        CONSTANT inl4 : sequence := (0, 1, 2, 3,-4,-3,-2,-1);
        CONSTANT inl5 : sequence := (0,-1, 2, 1,-4,-5,-2,-3);
        CONSTANT inl6 : sequence := (0, 1,-2,-1,-4,-3,-6,-5);
        CONSTANT inl7 : sequence := (0,-1,-2,-3,-4,-5,-6,-7);
        CONSTANT inl  : seqtab   := (inl0, inl1, inl2, inl3, inl4, inl5, inl6,
                               inl7);

        --memory definition
        TYPE MemStore IS ARRAY (0 TO MemSize) OF integer RANGE -2 TO MaxData;
        TYPE MemBlock IS ARRAY (0 TO BankNum) OF MemStore;
        SHARED VARIABLE Mem    : MemBlock;

        --mode registers
        SHARED VARIABLE MR0 : std_logic_vector(15 DOWNTO 0) := (OTHERS => '0');
        SHARED VARIABLE MR1 : std_logic_vector(15 DOWNTO 0);
        SHARED VARIABLE MR2 : std_logic_vector(15 DOWNTO 0);
        SHARED VARIABLE MR3 : std_logic_vector(15 DOWNTO 0);

        SHARED VARIABLE burst_len : natural RANGE 4 TO 8;--burst length

        SHARED VARIABLE active_forbid : boolean := FALSE;--more than 4 active
                                                         --commands during tFAW

        --bank, row and column of scheduled read or write operation
        SHARED VARIABLE current_bank : natural RANGE 0 TO BankNum;
        SHARED VARIABLE current_row : natural RANGE 0 TO RowNum;
        SHARED VARIABLE current_column : natural RANGE 0 TO ColNum;

        --bank, row and column of read operation that starts
        SHARED VARIABLE read_bank : natural RANGE 0 TO BankNum;
        SHARED VARIABLE read_row : natural RANGE 0 TO RowNum;
        SHARED VARIABLE read_column : natural RANGE 0 TO ColNum;
        -- WRITE LEVELING PROCEDURE
        SIGNAL WL_on : boolean := FALSE;--Write Leveling enabled
        SHARED VARIABLE ODTLOFF : boolean := FALSE;

        TYPE write_sch_type IS ARRAY (0 TO 10) OF boolean;
        TYPE write_sch_bank_type IS ARRAY (0 TO BankNum) OF write_sch_type;
        --all scheduled reads within all banks
        SHARED VARIABLE read_sch : write_sch_bank_type :=
                                                  (OTHERS => (OTHERS => FALSE));
        --reads that should be preceeded by preamble
        SHARED VARIABLE preamble : write_sch_bank_type :=
                                                  (OTHERS => (OTHERS => TRUE));

        TYPE wait_read_type IS ARRAY (0 TO 10) OF std_ulogic;
        TYPE wait_read_bank_type IS ARRAY (0 TO BankNum) OF wait_read_type;
        --wait_read triggers process that counts remaining cycles to the
        --beggining of scheduled read when aditive latency has elapsed, and
        --read_delay keeps information of number of remaining cycles
        SIGNAL wait_read : wait_read_bank_type;
        SHARED VARIABLE read_delay : natural RANGE 0 TO 10;

        --needed for check if all rows were refreshed during refresh period
        SIGNAL Ref_per_start : std_ulogic := '0';
        SIGNAL Ref_per_expired : std_ulogic := '0';

        SHARED VARIABLE CK_rise : time := 0 ns;
        SHARED VARIABLE CK_period : time := 0 ns;

        TYPE Bank_state_type IS (precharged, refreshing, MRsetting, activating,
                                 active, reading, readingAP, writting,
                                 writtingAP, precharging, prechall,ZQ_calib);
        TYPE Bank_state_array_type IS ARRAY (0 TO BankNum) OF Bank_state_type;
        SHARED VARIABLE Curr_bank_state : Bank_state_array_type;
        SHARED VARIABLE Next_bank_state : Bank_state_array_type;

        SHARED VARIABLE SR_cond : boolean := FALSE;--self refresh can be entered
        SIGNAL SelfRefresh : boolean := FALSE;--self refresh active
        --Partial self refresh active
        SIGNAL PartialSelfRefresh : boolean := FALSE;
        SIGNAL SR_exit : boolean := FALSE;--CKE high, self refresh exit
        SHARED VARIABLE SR_enter_cycle : boolean := FALSE;--clock can be
                                                          --turned off

        SIGNAL Pre_PD : boolean := FALSE;--precharge power down active
        SIGNAL Act_PD : boolean := FALSE;--active power down active
        SHARED VARIABLE Read_Start : boolean := FALSE;--read burst in progress,
        SIGNAL ReadStart : boolean := FALSE;          --no pd entry

        SIGNAL Reset : boolean := FALSE;--reset function active
        SIGNAL RST              : std_logic := '1';
        SHARED VARIABLE Reset_enter_cycle : boolean := FALSE;--clocks can be
                                                             --turned off
        SIGNAL SimulationEnd : boolean := FALSE;

        SHARED VARIABLE mrs_cnt : natural;

        SIGNAL mrs_active : std_logic := '0';

        SIGNAL preamble_check : boolean := FALSE;
        SIGNAL postamble_check : boolean := FALSE;

        FUNCTION bool_to_nat(tm : boolean)
        RETURN natural IS
            VARIABLE Temp : natural;
        BEGIN
            Temp := 0;
            IF tm THEN
                Temp := 1;
            END IF;
            RETURN Temp;
        END bool_to_nat;

    BEGIN

    RST <= RESETNeg AFTER 100 ns;

    CK_DLL: PROCESS(CKDiff)
        VARIABLE Previous   : time := 0 ns;
        VARIABLE TmpPer     : time := 0 ns;
    BEGIN
        IF rising_edge(CKDiff) THEN
            TmpPer := NOW - Previous;
            IF TmpPer > 0 ns THEN
                CKPeriod <= TmpPer;
            END IF;
            Previous := NOW;
            CKHalfPer <= CKPeriod / 2;
            CKDLLDelay <= CKPeriod + tpd_CK_DQ1;
        END IF;
    END PROCESS CK_DLL;

    CK_temp: PROCESS(CKDiff) -- generating internal clock from DLL
    BEGIN
        CKtemp <= NOT CKtemp AFTER CKHalfPer;
    END PROCESS CK_temp;

    CKInt <= TRANSPORT CKtemp AFTER CKDLLDelay;

    Clock_init: PROCESS(CK)
    BEGIN
        IF rising_edge(CK) AND NOT PoweredUp THEN
            CK_COUNT <= CK_COUNT + 1;
        END IF;
    END PROCESS Clock_init;

    Power_up: PROCESS(CK_stable,CK_COUNT)
    BEGIN
        IF CK_stable AND (CK_COUNT >= 5) AND NOT PoweredUp THEN
            PoweredUp <= TRUE;
        END IF;
    END PROCESS Power_up;

    Init_d: PROCESS(In_d)
    BEGIN
        IF In_d THEN
            Init_delay <= TRUE AFTER tdevice_tXPR;
        ELSE
            Init_delay <= FALSE;
        END IF;
    END PROCESS Init_d;

    Init_d1: PROCESS(In_d1)
    BEGIN
        IF In_d1 THEN
            Init_delay1 <= TRUE AFTER tdevice_tMRD;
        ELSE
            Init_delay1 <= FALSE;
        END IF;
    END PROCESS Init_d1;

    Init_d2: PROCESS(In_d2)
    BEGIN
        IF In_d2 THEN
            Init_delay2 <= TRUE AFTER tdevice_tZQINIT;
        ELSE
            Init_delay2 <= FALSE;
        END IF;
    END PROCESS Init_d2;

    Init_d3: PROCESS(In_d3)
    BEGIN
        IF In_d3 THEN
            Init_delay3 <= TRUE AFTER tdevice_tZQOPER;
        ELSE
            Init_delay3 <= FALSE;
        END IF;
    END PROCESS Init_d3;

    Init_d4: PROCESS(In_d4)
    BEGIN
        IF In_d4 THEN
            Init_delay4 <= TRUE AFTER tdevice_tZQCS;
        ELSE
            Init_delay4 <= FALSE;
        END IF;
    END PROCESS Init_d4;

    PROCESS (tMOD_in_tmp)
    BEGIN
        IF rising_edge(tMOD_in_tmp) THEN
            tMOD_out_tmp <= '0', '1' AFTER tdevice_tMOD;
        END IF;
    END PROCESS;

    DLLdelay: PROCESS(DLL_delay, CKDiff)
        VARIABLE cnt : natural;
    BEGIN
        IF rising_edge(DLL_delay) THEN
            cnt := 0;
            DLL_delay_elapsed <= FALSE;
        ELSIF rising_edge(CKDiff) AND NOT DLL_delay_elapsed THEN
            cnt := cnt + 1;
            IF cnt = 511 THEN
                DLL_delay_elapsed <= TRUE;
            END IF;
        END IF;
    END PROCESS DLLdelay;

    ----------------------------------------------------------------------------
    -- Vital Behavior Process
    ----------------------------------------------------------------------------
    VITALBehaviour: PROCESS(CKDiff, DQSDiff, DQSIn, DQIn,
                            DM, ODT, CKE, CSNeg, RASNeg, CASNeg,
                            WENeg, BAIn, AIn, RESETNeg)

        -- Timing Check Variables
        VARIABLE Tviol_DQ0_DQS     : X01 := '0';
        VARIABLE TD_DQ0_DQS        : VitalTimingDataType;

        VARIABLE Tviol_DQ0_DQS1    : X01 := '0';
        VARIABLE TD_DQ0_DQS1       : VitalTimingDataType;

        VARIABLE Tviol_DQ1_DQS     : X01 := '0';
        VARIABLE TD_DQ1_DQS        : VitalTimingDataType;

        VARIABLE Tviol_DQ1_DQS1    : X01 := '0';
        VARIABLE TD_DQ1_DQS1       : VitalTimingDataType;

        VARIABLE Tviol_DM0_DQS     : X01 := '0';
        VARIABLE TD_DM0_DQS        : VitalTimingDataType;

        VARIABLE Tviol_DM0_DQS1    : X01 := '0';
        VARIABLE TD_DM0_DQS1       : VitalTimingDataType;

        VARIABLE Tviol_DM1_DQS     : X01 := '0';
        VARIABLE TD_DM1_DQS        : VitalTimingDataType;

        VARIABLE Tviol_DM1_DQS1    : X01 := '0';
        VARIABLE TD_DM1_DQS1       : VitalTimingDataType;