📄 mcm63z818.ftm

📁 vhdl cod for ram.For sp3e
💻 FTM
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<!DOCTYPE FTML SYSTEM "ftml.dtd"><FTML><HEAD><TITLE>FMF Timing for MCM63Z818 Parts</TITLE><REVISION.HISTORY>version: |  author:  | mod date: | changes made:  V1.0     R. Munden   99 AUG 06  Initial release  V1.1     R. Munden   08 JUN 07  Changed port name DQ0 to DQA0</REVISION.HISTORY></HEAD><BODY><TIMESCALE>1ns</TIMESCALE><MODEL>MCM63Z818<FMFTIME>CY7C1352-143AL<SOURCE>Cypress Semiconductor Data Sheet April 29, 1998</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, CL=5pF, Ta=0 to 70 Celsius</COMMENT><COMMENT> Typical values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQA0 (2.0:3.4:4.0) (2.0:3.4:4.0) (1.5:3.0:3.5) (2.0:3.4:4.0) (1.5:3.0:3.5) (2.0:3.4:4.0))     (IOPATH OENeg DQA0 () () (1.5:3.4:4.0) (0.0:3.4:4.0) (1.5:3.4:4.0) (0.0:3.4:4.0))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (7.0))    (WIDTH  (posedge CLK) (2.0))    (WIDTH  (negedge CLK) (2.0))    (SETUP A0 CLK (2.0))    (SETUP CLKENNeg CLK (2.0))    (SETUP DQA0 CLK (1.7))    (SETUP R CLK (2.0))    (SETUP ADV CLK (2.0))    (SETUP CE2 CLK (2.0))    (SETUP BWANeg CLK (2.0))    (HOLD A0 CLK (0.5))    (HOLD CLKENNeg CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD R CLK (0.5))    (HOLD ADV CLK (0.5))    (HOLD CE2 CLK (0.5))    (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>CY7C1352-133AL<SOURCE>Cypress Semiconductor Data Sheet April 29, 1998</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, CL=5pF, Ta=0 to 70 Celsius</COMMENT><COMMENT> Typical values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQA0 (2.0:3.5:4.2) (2.0:3.5:4.2) (1.5:3.0:3.5) (2.0:3.5:4.2) (1.5:3.0:3.5) (2.0:3.5:4.2))     (IOPATH OENeg DQA0 () () (1.5:3.5:4.2) (0.0:3.5:4.2) (1.5:3.5:4.2) (0.0:3.5:4.2))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (7.5))    (WIDTH  (posedge CLK) (2.5))    (WIDTH  (negedge CLK) (2.5))    (SETUP A0 CLK (2.0))    (SETUP CLKENNeg CLK (2.0))    (SETUP DQA0 CLK (1.7))    (SETUP R CLK (2.0))    (SETUP ADV CLK (2.0))    (SETUP CE2 CLK (2.0))    (SETUP BWANeg CLK (2.0))    (HOLD A0 CLK (0.5))    (HOLD CLKENNeg CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD R CLK (0.5))    (HOLD ADV CLK (0.5))    (HOLD CE2 CLK (0.5))    (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>CY7C1352-100AL<SOURCE>Cypress Semiconductor Data Sheet April 29, 1998</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, CL=5pF, Ta=0 to 70 Celsius</COMMENT><COMMENT> Typical values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQA0 (2.0:3.8:5.0) (2.0:3.8:5.0) (1.5:3.0:3.5) (2.0:3.8:5.0) (1.5:3.0:3.5) (2.0:3.8:5.0))     (IOPATH OENeg DQA0 () () (1.5:3.8:5.0) (0.0:3.8:5.0) (1.5:3.8:5.0) (0.0:3.8:5.0))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (10))    (WIDTH  (posedge CLK) (3.5))    (WIDTH  (negedge CLK) (3.5))    (SETUP A0 CLK (2.2))    (SETUP CLKENNeg CLK (2.2))    (SETUP DQA0 CLK (2.0))    (SETUP R CLK (2.2))    (SETUP ADV CLK (2.2))    (SETUP CE2 CLK (2.2))    (SETUP BWANeg CLK (2.2))    (HOLD A0 CLK (0.5))    (HOLD CLKENNeg CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD R CLK (0.5))    (HOLD ADV CLK (0.5))    (HOLD CE2 CLK (0.5))    (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>CY7C1352-80AL<SOURCE>Cypress Semiconductor Data Sheet April 29, 1998</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, CL=5pF, Ta=0 to 70 Celsius</COMMENT><COMMENT> Typical values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQA0 (2.0:5.0:7.0) (2.0:5.0:7.0) (1.5:3.8:5.0) (2.0:5.0:7.0) (1.5:3.8:5.0) (2.0:5.0:7.0))     (IOPATH OENeg DQA0 () () (1.5:5.0:7.0) (0.0:5.0:7.0) (1.5:5.0:7.0) (0.0:5.0:7.0))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (12.5))    (WIDTH  (posedge CLK) (4.0))    (WIDTH  (negedge CLK) (4.0))    (SETUP A0 CLK (2.5))    (SETUP CLKENNeg CLK (2.5))    (SETUP DQA0 CLK (2.5))    (SETUP R CLK (2.5))    (SETUP ADV CLK (2.5))    (SETUP CE2 CLK (2.5))    (SETUP BWANeg CLK (2.5))    (HOLD A0 CLK (1.0))    (HOLD CLKENNeg CLK (1.0))    (HOLD DQA0 CLK (1.0))    (HOLD R CLK (1.0))    (HOLD ADV CLK (1.0))    (HOLD CE2 CLK (1.0))    (HOLD BWANeg CLK (1.0)) )</TIMING></FMFTIME><FMFTIME>MT55L256L18PT-6<SOURCE>Micron Technology MT55L256L18P.p65 Rev. 3/99</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, CL=5pF, Ta=0 to 70 Celsius</COMMENT><COMMENT> Typical values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQA0 (1.5:3.0:3.5) (1.5:3.0:3.5) (1.5:3.0:3.5) (1.5:3.0:3.5) (1.5:3.0:3.5) (1.5:3.0:3.5))     (IOPATH OENeg DQA0 () () (1.5:3.0:3.5) (0.0:2.1:3.5) (1.5:3.0:3.5) (0.0:2.1:3.5))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (6.0))    (WIDTH  (posedge CLK) (1.7))    (WIDTH  (negedge CLK) (1.7))    (SETUP A0 CLK (1.5))    (SETUP CLKENNeg CLK (1.5))    (SETUP DQA0 CLK (1.5))    (SETUP R CLK (1.5))    (SETUP ADV CLK (1.5))    (SETUP CE2 CLK (1.5))    (SETUP BWANeg CLK (1.5))    (HOLD A0 CLK (0.5))    (HOLD CLKENNeg CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD R CLK (0.5))    (HOLD ADV CLK (0.5))    (HOLD CE2 CLK (0.5))    (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>MT55L256L18PT-7.5<SOURCE>Micron Technology MT55L256L18P.p65 Rev. 3/99</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, CL=5pF, Ta=0 to 70 Celsius</COMMENT><COMMENT> Typical values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQA0 (1.5:3.5:4.2) (1.5:3.5:4.2) (1.5:3.0:3.5) (1.5:3.5:4.2) (1.5:3.0:3.5) (1.5:3.5:4.2))     (IOPATH OENeg DQA0 () () (1.5:3.5:4.2) (0.0:2.1:4.2) (1.5:3.5:4.2) (0.0:2.1:4.2))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (7.5))    (WIDTH  (posedge CLK) (2.0))    (WIDTH  (negedge CLK) (2.0))    (SETUP A0 CLK (1.7))    (SETUP CLKENNeg CLK (1.7))    (SETUP DQA0 CLK (1.7))    (SETUP R CLK (1.7))    (SETUP ADV CLK (1.7))    (SETUP CE2 CLK (1.7))    (SETUP BWANeg CLK (1.7))    (HOLD A0 CLK (0.5))    (HOLD CLKENNeg CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD R CLK (0.5))    (HOLD ADV CLK (0.5))    (HOLD CE2 CLK (0.5))    (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>MT55L256L18PT-10<SOURCE>Micron Technology MT55L256L18P.p65 Rev. 3/99</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, CL=5pF, Ta=0 to 70 Celsius</COMMENT><COMMENT> Typical values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQA0 (1.5:4.0:5.0) (1.5:4.0:5.0) (1.5:3.0:3.5) (1.5:4.0:5.0) (1.5:3.0:3.5) (1.5:4.0:5.0))     (IOPATH OENeg DQA0 () () (1.5:4.0:5.0) (0.0:2.5:5.0) (1.5:4.0:5.0) (0.0:2.5:5.0))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (10))    (WIDTH  (posedge CLK) (3.2))    (WIDTH  (negedge CLK) (3.2))    (SETUP A0 CLK (2.0))    (SETUP CLKENNeg CLK (2.0))    (SETUP DQA0 CLK (2.0))    (SETUP R CLK (2.0))    (SETUP ADV CLK (2.0))    (SETUP CE2 CLK (2.0))    (SETUP BWANeg CLK (2.0))    (HOLD A0 CLK (0.5))    (HOLD CLKENNeg CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD R CLK (0.5))    (HOLD ADV CLK (0.5))    (HOLD CE2 CLK (0.5))    (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>MCM63Z818TQ143<SOURCE>Motorola Semiconductor MCM63Z736/D Rev 5 7/2/99</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, CL=5pF, Ta=0 to 70 Celsius</COMMENT><COMMENT> Typical values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQA0 (1.5:3.4:4.0) (1.5:3.4:4.0) (1.5:3.4:4.0) (1.5:3.4:4.0) (1.5:3.4:4.0) (1.5:3.4:4.0))     (IOPATH OENeg DQA0 () () (1.5:3.0:3.5) (0.0:3.4:4.0) (1.5:3.0:3.5) (0.0:3.4:4.0))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (7.0))    (WIDTH  (posedge CLK) (2.8))    (WIDTH  (negedge CLK) (2.8))    (SETUP A0 CLK (2.0))    (SETUP CLKENNeg CLK (2.0))    (SETUP DQA0 CLK (1.7))    (SETUP R CLK (2.0))    (SETUP ADV CLK (2.0))    (SETUP CE2 CLK (2.0))    (SETUP BWANeg CLK (2.0))    (HOLD A0 CLK (0.5))    (HOLD CLKENNeg CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD R CLK (0.5))    (HOLD ADV CLK (0.5))    (HOLD CE2 CLK (0.5))    (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>MCM63Z818TQ133<SOURCE>Motorola Semiconductor MCM63Z736/D Rev 5 7/2/99</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, CL=5pF, Ta=0 to 70 Celsius</COMMENT><COMMENT> Typical values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQA0 (1.5:3.5:4.2) (1.5:3.5:4.2) (1.5:3.5:4.2) (1.5:3.5:4.2) (1.5:3.5:4.2) (1.5:3.5:4.2))     (IOPATH OENeg DQA0 () () (1.5:3.0:3.5) (0.0:3.5:4.2) (1.5:3.0:3.5) (0.0:3.5:4.2))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (7.5))    (WIDTH  (posedge CLK) (3.0))    (WIDTH  (negedge CLK) (3.0))    (SETUP A0 CLK (2.0))    (SETUP CLKENNeg CLK (2.0))    (SETUP DQA0 CLK (1.7))    (SETUP R CLK (2.0))    (SETUP ADV CLK (2.0))    (SETUP CE2 CLK (2.0))    (SETUP BWANeg CLK (2.0))    (HOLD A0 CLK (0.5))    (HOLD CLKENNeg CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD R CLK (0.5))    (HOLD ADV CLK (0.5))    (HOLD CE2 CLK (0.5))    (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>MCM63Z818TQ100<SOURCE>Motorola Semiconductor MCM63Z736/D Rev 5 7/2/99</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, CL=5pF, Ta=0 to 70 Celsius</COMMENT><COMMENT> Typical values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH CLK DQA0 (1.5:4.0:5.0) (1.5:4.0:5.0) (1.5:4.0:5.0) (1.5:4.0:5.0) (1.5:4.0:5.0) (1.5:4.0:5.0))     (IOPATH OENeg DQA0 () () (1.5:3.0:3.5) (0.0:4.0:5.0) (1.5:3.0:3.5) (0.0:4.0:5.0))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (10.0))    (WIDTH  (posedge CLK) (4.0))    (WIDTH  (negedge CLK) (4.0))    (SETUP A0 CLK (2.2))    (SETUP CLKENNeg CLK (2.2))    (SETUP DQA0 CLK (2.0))    (SETUP R CLK (2.2))    (SETUP ADV CLK (2.2))    (SETUP CE2 CLK (2.2))    (SETUP BWANeg CLK (2.2))    (HOLD A0 CLK (0.5))    (HOLD CLKENNeg CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD R CLK (0.5))    (HOLD ADV CLK (0.5))    (HOLD CE2 CLK (0.5))    (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME></BODY></FTML>
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