cy7c1361.vhd

vhdl cod for ram.For sp3e

    SIGNAL CLK_ipd             : std_ulogic := 'U';
    SIGNAL CENeg_ipd           : std_ulogic := 'U';
    SIGNAL CE2_ipd             : std_ulogic := 'U';
    SIGNAL OENeg_ipd           : std_ulogic := 'U';
    SIGNAL CE2Neg_ipd          : std_ulogic := 'U';
    SIGNAL ADVNeg_ipd          : std_ulogic := 'U';
    SIGNAL ADSPNeg_ipd         : std_ulogic := 'U';
    SIGNAL ADSCNeg_ipd         : std_ulogic := 'U';
    SIGNAL MODE_ipd            : std_ulogic := 'U';
    SIGNAL ZZ_ipd              : std_ulogic := 'U';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_01 : VitalWireDelay (A0_ipd,      A0,      tipd_A0);
        w_02 : VitalWireDelay (A1_ipd,      A1,      tipd_A1);
        w_03 : VitalWireDelay (A2_ipd,      A2,      tipd_A2);
        w_04 : VitalWireDelay (A3_ipd,      A3,      tipd_A3);
        w_05 : VitalWireDelay (A4_ipd,      A4,      tipd_A4);
        w_06 : VitalWireDelay (A5_ipd,      A5,      tipd_A5);
        w_07 : VitalWireDelay (A6_ipd,      A6,      tipd_A6);
        w_08 : VitalWireDelay (A7_ipd,      A7,      tipd_A7);
        w_09 : VitalWireDelay (A8_ipd,      A8,      tipd_A8);
        w_10 : VitalWireDelay (A9_ipd,      A9,      tipd_A9);
        w_11 : VitalWireDelay (A10_ipd,     A10,     tipd_A10);
        w_12 : VitalWireDelay (A11_ipd,     A11,     tipd_A11);
        w_13 : VitalWireDelay (A12_ipd,     A12,     tipd_A12);
        w_14 : VitalWireDelay (A13_ipd,     A13,     tipd_A13);
        w_15 : VitalWireDelay (A14_ipd,     A14,     tipd_A14);
        w_16 : VitalWireDelay (A15_ipd,     A15,     tipd_A15);
        w_17 : VitalWireDelay (A16_ipd,     A16,     tipd_A16);
        w_18 : VitalWireDelay (A17_ipd,     A17,     tipd_A17);
        w_19 : VitalWireDelay (DQA0_ipd,    DQA0,    tipd_DQA0);
        w_20 : VitalWireDelay (DQA1_ipd,    DQA1,    tipd_DQA1);
        w_21 : VitalWireDelay (DQA2_ipd,    DQA2,    tipd_DQA2);
        w_22 : VitalWireDelay (DQA3_ipd,    DQA3,    tipd_DQA3);
        w_23 : VitalWireDelay (DQA4_ipd,    DQA4,    tipd_DQA4);
        w_24 : VitalWireDelay (DQA5_ipd,    DQA5,    tipd_DQA5);
        w_25 : VitalWireDelay (DQA6_ipd,    DQA6,    tipd_DQA6);
        w_26 : VitalWireDelay (DQA7_ipd,    DQA7,    tipd_DQA7);
        w_27 : VitalWireDelay (DQA8_ipd,    DQA8,    tipd_DQA8);
        w_28 : VitalWireDelay (DQB0_ipd,    DQB0,    tipd_DQB0);
        w_29 : VitalWireDelay (DQB1_ipd,    DQB1,    tipd_DQB1);
        w_30 : VitalWireDelay (DQB2_ipd,    DQB2,    tipd_DQB2);
        w_31 : VitalWireDelay (DQB3_ipd,    DQB3,    tipd_DQB3);
        w_32 : VitalWireDelay (DQB4_ipd,    DQB4,    tipd_DQB4);
        w_33 : VitalWireDelay (DQB5_ipd,    DQB5,    tipd_DQB5);
        w_34 : VitalWireDelay (DQB6_ipd,    DQB6,    tipd_DQB6);
        w_35 : VitalWireDelay (DQB7_ipd,    DQB7,    tipd_DQB7);
        w_36 : VitalWireDelay (DQB8_ipd,    DQB8,    tipd_DQB8);
        w_37 : VitalWireDelay (DQC0_ipd,    DQC0,    tipd_DQC0);
        w_38 : VitalWireDelay (DQC1_ipd,    DQC1,    tipd_DQC1);
        w_39 : VitalWireDelay (DQC2_ipd,    DQC2,    tipd_DQC2);
        w_40 : VitalWireDelay (DQC3_ipd,    DQC3,    tipd_DQC3);
        w_41 : VitalWireDelay (DQC4_ipd,    DQC4,    tipd_DQC4);
        w_42 : VitalWireDelay (DQC5_ipd,    DQC5,    tipd_DQC5);
        w_43 : VitalWireDelay (DQC6_ipd,    DQC6,    tipd_DQC6);
        w_44 : VitalWireDelay (DQC7_ipd,    DQC7,    tipd_DQC7);
        w_45 : VitalWireDelay (DQC8_ipd,    DQC8,    tipd_DQC8);
        w_46 : VitalWireDelay (DQD0_ipd,    DQD0,    tipd_DQD0);
        w_47 : VitalWireDelay (DQD1_ipd,    DQD1,    tipd_DQD1);
        w_48 : VitalWireDelay (DQD2_ipd,    DQD2,    tipd_DQD2);
        w_49 : VitalWireDelay (DQD3_ipd,    DQD3,    tipd_DQD3);
        w_50 : VitalWireDelay (DQD4_ipd,    DQD4,    tipd_DQD4);
        w_51 : VitalWireDelay (DQD5_ipd,    DQD5,    tipd_DQD5);
        w_52 : VitalWireDelay (DQD6_ipd,    DQD6,    tipd_DQD6);
        w_53 : VitalWireDelay (DQD7_ipd,    DQD7,    tipd_DQD7);
        w_54 : VitalWireDelay (DQD8_ipd,    DQD8,    tipd_DQD8);
        w_55 : VitalWireDelay (BWANeg_ipd,  BWANeg,  tipd_BWANeg);
        w_56 : VitalWireDelay (BWBNeg_ipd,  BWBNeg,  tipd_BWBNeg);
        w_57 : VitalWireDelay (BWCNeg_ipd,  BWCNeg,  tipd_BWCNeg);
        w_58 : VitalWireDelay (BWDNeg_ipd,  BWDNeg,  tipd_BWDNeg);
        w_59 : VitalWireDelay (GWNeg_ipd,   GWNeg,   tipd_GWNeg);
        w_60 : VitalWireDelay (BWENeg_ipd,  BWENeg,  tipd_BWENeg);
        w_61 : VitalWireDelay (CLK_ipd,     CLK,     tipd_CLK);
        w_62 : VitalWireDelay (CENeg_ipd,   CENeg,   tipd_CENeg);
        w_63 : VitalWireDelay (CE2_ipd,     CE2,     tipd_CE2);
        w_64 : VitalWireDelay (CE2Neg_ipd,  CE2Neg,  tipd_CE2Neg);
        w_65 : VitalWireDelay (OENeg_ipd,   OENeg,   tipd_OENeg);
        w_66 : VitalWireDelay (ADVNeg_ipd,  ADVNeg,  tipd_ADVNeg);
        w_67 : VitalWireDelay (ADSPNeg_ipd, ADSPNeg, tipd_ADSPNeg);
        w_68 : VitalWireDelay (ADSCNeg_ipd, ADSCNeg, tipd_ADSCNeg);
        w_69 : VitalWireDelay (MODE_ipd,    MODE,    tipd_MODE);
        w_70 : VitalWireDelay (ZZ_ipd,      ZZ,      tipd_ZZ);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Main Behavior Block
    ----------------------------------------------------------------------------
    Behavior: BLOCK

        PORT (
            BWANIn          : IN    std_ulogic := 'U';
            BWBNIn          : IN    std_ulogic := 'U';
            BWCNIn          : IN    std_ulogic := 'U';
            BWDNIn          : IN    std_ulogic := 'U';
            GWNIn           : IN    std_ulogic := 'U';
            BWENIn          : IN    std_ulogic := 'U';
            DatAIn          : IN    std_logic_vector(8 downto 0);
            DatBIn          : IN    std_logic_vector(8 downto 0);
            DatCIn          : IN    std_logic_vector(8 downto 0);
            DatDIn          : IN    std_logic_vector(8 downto 0);
            DataOut         : OUT   std_logic_vector(35 downto 0)
                                                     := (others => 'Z');
            CLKIn           : IN    std_ulogic := 'U';
            AddressIn       : IN    std_logic_vector(17 downto 0);
            OENegIn         : IN    std_ulogic := 'U';
            ADVNIn          : IN    std_ulogic := 'U';
            ADSPNIn         : IN    std_ulogic := 'U';
            ADSCNIn         : IN    std_ulogic := 'U';
            MODEIn          : IN    std_ulogic := 'U';
            ZZIn            : IN    std_ulogic := 'U';
            CE2In           : IN    std_ulogic := 'U';
            CENegIn         : IN    std_ulogic := 'U';
            CE2NegIn        : IN    std_ulogic := 'U'
        );
        PORT MAP (
            BWANIn        =>  BWANeg_ipd,
            BWBNIn        =>  BWBNeg_ipd,
            BWCNIn        =>  BWCNeg_ipd,
            BWDNIn        =>  BWDNeg_ipd,
            GWNIn         =>  GWNeg_ipd,
            BWENIn        =>  BWENeg_ipd,
            CLKIn         =>  CLK_ipd,
            OENegIn       =>  OENeg_ipd,
            ADVNIn        =>  ADVNeg_ipd,
            ADSPNIn       =>  ADSPNeg_ipd,
            ADSCNIn       =>  ADSCNeg_ipd,
            MODEIn        =>  MODE_ipd,
            ZZIn          =>  ZZ_ipd,
            CE2In         =>  CE2_ipd,
            CENegIn       =>  CENeg_ipd,
            CE2NegIn      =>  CE2Neg_ipd,
            DataOut(0)    =>  DQA0,
            DataOut(1)    =>  DQA1,
            DataOut(2)    =>  DQA2,
            DataOut(3)    =>  DQA3,
            DataOut(4)    =>  DQA4,
            DataOut(5)    =>  DQA5,
            DataOut(6)    =>  DQA6,
            DataOut(7)    =>  DQA7,
            DataOut(8)    =>  DQA8,
            DataOut(9)    =>  DQB0,
            DataOut(10)   =>  DQB1,
            DataOut(11)   =>  DQB2,
            DataOut(12)   =>  DQB3,
            DataOut(13)   =>  DQB4,
            DataOut(14)   =>  DQB5,
            DataOut(15)   =>  DQB6,
            DataOut(16)   =>  DQB7,
            DataOut(17)   =>  DQB8,
            DataOut(18)   =>  DQC0,
            DataOut(19)   =>  DQC1,
            DataOut(20)   =>  DQC2,
            DataOut(21)   =>  DQC3,
            DataOut(22)   =>  DQC4,
            DataOut(23)   =>  DQC5,
            DataOut(24)   =>  DQC6,
            DataOut(25)   =>  DQC7,
            DataOut(26)   =>  DQC8,
            DataOut(27)   =>  DQD0,
            DataOut(28)   =>  DQD1,
            DataOut(29)   =>  DQD2,
            DataOut(30)   =>  DQD3,
            DataOut(31)   =>  DQD4,
            DataOut(32)   =>  DQD5,
            DataOut(33)   =>  DQD6,
            DataOut(34)   =>  DQD7,
            DataOut(35)   =>  DQD8,
            DatAIn(0)     =>  DQA0_ipd,
            DatAIn(1)     =>  DQA1_ipd,
            DatAIn(2)     =>  DQA2_ipd,
            DatAIn(3)     =>  DQA3_ipd,
            DatAIn(4)     =>  DQA4_ipd,
            DatAIn(5)     =>  DQA5_ipd,
            DatAIn(6)     =>  DQA6_ipd,
            DatAIn(7)     =>  DQA7_ipd,
            DatAIn(8)     =>  DQA8_ipd,
            DatBIn(0)     =>  DQB0_ipd,
            DatBIn(1)     =>  DQB1_ipd,
            DatBIn(2)     =>  DQB2_ipd,
            DatBIn(3)     =>  DQB3_ipd,
            DatBIn(4)     =>  DQB4_ipd,
            DatBIn(5)     =>  DQB5_ipd,
            DatBIn(6)     =>  DQB6_ipd,
            DatBIn(7)     =>  DQB7_ipd,
            DatBIn(8)     =>  DQB8_ipd,
            DatCIn(0)     =>  DQC0_ipd,
            DatCIn(1)     =>  DQC1_ipd,
            DatCIn(2)     =>  DQC2_ipd,
            DatCIn(3)     =>  DQC3_ipd,
            DatCIn(4)     =>  DQC4_ipd,
            DatCIn(5)     =>  DQC5_ipd,
            DatCIn(6)     =>  DQC6_ipd,
            DatCIn(7)     =>  DQC7_ipd,
            DatCIn(8)     =>  DQC8_ipd,
            DatDIn(0)     =>  DQD0_ipd,
            DatDIn(1)     =>  DQD1_ipd,
            DatDIn(2)     =>  DQD2_ipd,
            DatDIn(3)     =>  DQD3_ipd,
            DatDIn(4)     =>  DQD4_ipd,
            DatDIn(5)     =>  DQD5_ipd,
            DatDIn(6)     =>  DQD6_ipd,
            DatDIn(7)     =>  DQD7_ipd,
            DatDIn(8)     =>  DQD8_ipd,
            AddressIn(0)  =>  A0_ipd,
            AddressIn(1)  =>  A1_ipd,
            AddressIn(2)  =>  A2_ipd,
            AddressIn(3)  =>  A3_ipd,
            AddressIn(4)  =>  A4_ipd,
            AddressIn(5)  =>  A5_ipd,
            AddressIn(6)  =>  A6_ipd,
            AddressIn(7)  =>  A7_ipd,
            AddressIn(8)  =>  A8_ipd,
            AddressIn(9)  =>  A9_ipd,
            AddressIn(10) =>  A10_ipd,
            AddressIn(11) =>  A11_ipd,
            AddressIn(12) =>  A12_ipd,
            AddressIn(13) =>  A13_ipd,
            AddressIn(14) =>  A14_ipd,
            AddressIn(15) =>  A15_ipd,
            AddressIn(16) =>  A16_ipd,
            AddressIn(17) =>  A17_ipd
        );
        -- Type definition for state machine
        TYPE mem_state IS (desel,
                           begin_rdwr,
                           SPwrite,
                           SCwrite,
                           read
                          );

        SIGNAL state     : mem_state;

        TYPE sequence IS ARRAY (0 to 3) OF INTEGER RANGE -3 to 3;
        TYPE seqtab IS ARRAY (0 to 3) OF sequence;

        FILE mem_file    : text IS mem_file_name;

        CONSTANT il0 : sequence := (0, 1, 2, 3);
        CONSTANT il1 : sequence := (0, -1, 2, 1);
        CONSTANT il2 : sequence := (0, 1, -2, -1);
        CONSTANT il3 : sequence := (0, -1, -2, -3);
        CONSTANT il  : seqtab := (il0, il1, il2, il3);

        CONSTANT ln0 : sequence := (0, 1, 2, 3);
        CONSTANT ln1 : sequence := (0, 1, 2, -1);
        CONSTANT ln2 : sequence := (0, 1, -2, -1);
        CONSTANT ln3 : sequence := (0, -3, -2, -1);
        CONSTANT ln  : seqtab := (ln0, ln1, ln2, ln3);

        CONSTANT MemSize : INTEGER := 16#3FFFF#;  -- 256K
        CONSTANT MaxData : INTEGER := 16#1FF#;    -- 511

        -- Memory array declaration
        TYPE MemStore IS ARRAY (0 to MemSize) OF INTEGER
                         RANGE  -2 TO MaxData;

        SHARED VARIABLE MemDataA   : MemStore;
        SHARED VARIABLE MemDataB   : MemStore;
        SHARED VARIABLE MemDataC   : MemStore;
        SHARED VARIABLE MemDataD   : MemStore;

        -- Functionality Results Variables
        SHARED VARIABLE Violation  : X01 := '0';

        SHARED VARIABLE OBuf1      : std_logic_vector(35 DOWNTO 0)
                                   := (OTHERS => 'Z');

        SIGNAL Burst_Seq : seqtab := ln;
        SIGNAL D_zd      : std_logic_vector(35 DOWNTO 0);

        PROCEDURE ReadMem
            (RAddr     : IN natural)
        IS
        BEGIN
            IF MemDataA(RAddr) = -2 THEN
                OBuf1(8 downto 0) := (others => 'U');
            ELSIF MemDataA(RAddr) = -1 THEN
                OBuf1(8 downto 0) := (others => 'X');
            ELSE
                OBuf1(8 downto 0) := to_slv(MemDataA(RAddr),9);