idt70t3399.vhd

vhdl cod for ram.For sp3e

                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_RWR_CLK );

            VitalSetupHoldCheck (
                TestSignal      => ADSNegL,
                TestSignalName  => "ADS Left",
                RefSignal       => ClockL,
                RefSignalName   => "ClockL",
                SetupHigh       => tsetup_A0L_CLKL,
                SetupLow        => tsetup_A0L_CLKL,
                HoldHigh        => thold_A0L_CLKL,
                HoldLow         => thold_A0L_CLKL,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & PartID,
                TimingData      => TD_ADSL_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_ADSL_CLK );

            VitalSetupHoldCheck (
                TestSignal      => ADSNegR,
                TestSignalName  => "ADS Right",
                RefSignal       => ClockR,
                RefSignalName   => "ClockR",
                SetupHigh       => tsetup_A0L_CLKL,
                SetupLow        => tsetup_A0L_CLKL,
                HoldHigh        => thold_A0L_CLKL,
                HoldLow         => thold_A0L_CLKL,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & PartID,
                TimingData      => TD_ADSR_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_ADSR_CLK );

            VitalSetupHoldCheck (
                TestSignal      => CNTENNegL,
                TestSignalName  => "CntEn Left",
                RefSignal       => ClockL,
                RefSignalName   => "ClockL",
                SetupHigh       => tsetup_A0L_CLKL,
                SetupLow        => tsetup_A0L_CLKL,
                HoldHigh        => thold_A0L_CLKL,
                HoldLow         => thold_A0L_CLKL,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & PartID,
                TimingData      => TD_CNTL_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_CNTL_CLK );

            VitalSetupHoldCheck (
                TestSignal      => CNTENNegR,
                TestSignalName  => "CntEn Right",
                RefSignal       => ClockR,
                RefSignalName   => "ClockR",
                SetupHigh       => tsetup_A0L_CLKL,
                SetupLow        => tsetup_A0L_CLKL,
                HoldHigh        => thold_A0L_CLKL,
                HoldLow         => thold_A0L_CLKL,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & PartID,
                TimingData      => TD_CNTR_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_CNTR_CLK );

            VitalSetupHoldCheck (
                TestSignal      => REPEATNegL,
                TestSignalName  => "REPEAT Left",
                RefSignal       => ClockL,
                RefSignalName   => "ClockL",
                SetupHigh       => tsetup_A0L_CLKL,
                SetupLow        => tsetup_A0L_CLKL,
                HoldHigh        => thold_A0L_CLKL,
                HoldLow         => thold_A0L_CLKL,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & PartID,
                TimingData      => TD_RPTL_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_RPTL_CLK );

            VitalSetupHoldCheck (
                TestSignal      => REPEATNegR,
                TestSignalName  => "REPEAT Right",
                RefSignal       => ClockR,
                RefSignalName   => "ClockR",
                SetupHigh       => tsetup_A0L_CLKL,
                SetupLow        => tsetup_A0L_CLKL,
                HoldHigh        => thold_A0L_CLKL,
                HoldLow         => thold_A0L_CLKL,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & PartID,
                TimingData      => TD_RPTR_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_RPTR_CLK );

            VitalSetupHoldCheck (
                TestSignal      => TDI,
                TestSignalName  => "TDI",
                RefSignal       => TCK,
                RefSignalName   => "TCK",
                SetupHigh       => tsetup_TDI_TCK,
                SetupLow        => tsetup_TDI_TCK,
                HoldHigh        => thold_TDI_TCK,
                HoldLow         => thold_TDI_TCK,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & PartID,
                TimingData      => TD_TDI_TCK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_TDI_TCK );

            VitalPeriodPulseCheck (
                TestSignal      =>  ClockL,
                TestSignalName  =>  "Left Clock",
                Period          =>  tperiod_CLKL,
                PulseWidthLow   =>  tpw_CLKL_negedge,
                PulseWidthHigh  =>  tpw_CLKL_posedge,
                PeriodData      =>  PD_CLKP,
                XOn             =>  XOn,
                MsgOn           =>  MsgOn,
                Violation       =>  Pviol_CLKP,
                HeaderMsg       =>  InstancePath & PartID,
                CheckEnabled    =>  PLNegL='1' );

            VitalPeriodPulseCheck (
                TestSignal      =>  ClockL,
                TestSignalName  =>  "Left Clock",
                Period          =>  tperiod_CLKR,
                PulseWidthLow   =>  tpw_CLKR_negedge,
                PulseWidthHigh  =>  tpw_CLKR_posedge,
                PeriodData      =>  PD_CLKF,
                XOn             =>  XOn,
                MsgOn           =>  MsgOn,
                Violation       =>  Pviol_CLKF,
                HeaderMsg       =>  InstancePath & PartID,
                CheckEnabled    =>  PLNegL='0' );

            VitalPeriodPulseCheck (
                TestSignal      =>  ClockR,
                TestSignalName  =>  "Right Clock",
                Period          =>  tperiod_CLKL,
                PulseWidthLow   =>  tpw_CLKL_negedge,
                PulseWidthHigh  =>  tpw_CLKL_posedge,
                PeriodData      =>  PD_CLKP1,
                XOn             =>  XOn,
                MsgOn           =>  MsgOn,
                Violation       =>  Pviol_CLKP1,
                HeaderMsg       =>  InstancePath & PartID,
                CheckEnabled    =>  PLNegL='1' );

            VitalPeriodPulseCheck (
                TestSignal      =>  ClockL,
                TestSignalName  =>  "Left Clock",
                Period          =>  tperiod_CLKR,
                PulseWidthLow   =>  tpw_CLKR_negedge,
                PulseWidthHigh  =>  tpw_CLKR_posedge,
                PeriodData      =>  PD_CLKF1,
                XOn             =>  XOn,
                MsgOn           =>  MsgOn,
                Violation       =>  Pviol_CLKF1,
                HeaderMsg       =>  InstancePath & PartID,
                CheckEnabled    =>  PLNegL='0' );

            VitalPeriodPulseCheck (
                TestSignal      =>  TCK,
                TestSignalName  =>  "JTAG Clock",
                Period          =>  tperiod_TCK,
                PulseWidthLow   =>  tpw_TCK_negedge,
                PulseWidthHigh  =>  tpw_TCK_posedge,
                PeriodData      =>  PD_TCK,
                XOn             =>  XOn,
                MsgOn           =>  MsgOn,
                Violation       =>  Pviol_TCK,
                HeaderMsg       =>  InstancePath & PartID,
                CheckEnabled    =>  true );

            VitalPeriodPulseCheck (
                TestSignal      =>  TRSTNeg,
                TestSignalName  =>  "JTAG Reset",
                PulseWidthLow   =>  tpw_TRSTNeg_negedge,
                PeriodData      =>  PD_TRST,
                XOn             =>  XOn,
                MsgOn           =>  MsgOn,
                Violation       =>  Pviol_TRST,
                HeaderMsg       =>  InstancePath & PartID,
                CheckEnabled    =>  true );

             Violation := Tviol_AL_CLK OR Tviol_AR_CLK OR Tviol_DL_CLK OR
                          Tviol_DR_CLK OR Tviol_CEL_CLK OR Tviol_CER_CLK OR
                          Tviol_UBEL_CLK OR Tviol_UBER_CLK OR Tviol_RWL_CLK OR
                          Tviol_RWR_CLK OR Tviol_ADSL_CLK OR Tviol_ADSR_CLK
                          OR Tviol_CNTL_CLK OR Tviol_CNTR_CLK OR
                          Tviol_RPTL_CLK OR Tviol_RPTR_CLK OR Tviol_TDI_TCK OR
                          Pviol_CLKP OR Pviol_CLKF OR Pviol_CLKP1 OR
                          Pviol_CLKF1 OR Pviol_TCK OR Pviol_TRST OR
                          Tviol_LBEL_CLK OR Tviol_LBER_CLK;

            Viol <= Violation;

            ASSERT Violation = '0'
                REPORT InstancePath & partID & ": simulation may be" &
                " inaccurate due to timing violations"
                SEVERITY WARNING;

        END IF;

       -- Power Up & Reset JTAG
        IF NOW = 0 ns OR TRSTNeg = '0' THEN
            TAP_state := Test_Logic_Reset;
            IDReg := "00000000001100110101000001100111";
            IReg := "0010";
            Shift := false;
            UpdateIR := false;
            UpdateDR := false;
            Instruct <= idcode;
        END IF;

        -- TAP State Machine
        IF rising_edge(TCK) THEN
            CASE TAP_state IS
                WHEN Test_Logic_Reset =>
                    IF TMS = '1' THEN
                        TAP_state := Test_Logic_Reset;
                        IReg := "0010";
                        IDReg := "00000000001100110101000001100111";
                        Instruct <= idcode;
                    ELSE
                        TAP_state := Run_Test_Idle;
                    END IF;
                WHEN Run_Test_Idle =>
                    IF TMS = '1' THEN
                        TAP_state := Select_DR_Scan;
                    ELSE
                        TAP_state := Run_Test_Idle;
                    END IF;
                WHEN Select_DR_Scan =>
                    IF TMS = '1' THEN
                        TAP_state := Select_IR_Scan;
                    ELSE
                        TAP_state := Capture_DR;
                        CASE Instruct IS
                            WHEN extest =>
                                BSTmp := BSReg;
                            WHEN bypass =>
                                BYTmp := BYReg;
                            WHEN idcode =>
                                IDTmp := IDReg;
                            WHEN highz =>
                                BYTmp := BYReg;
                            WHEN sample_preload =>

--                                BSTmp(111) := INTNegR;
--                                BSTmp(110) := COLNegR;
                                BSTmp(109) := DataInL(17);
                                BSTmp(108) := DataInR(17);
                                BSTmp(107) := DataInL(16);
                                BSTmp(106) := DataInR(16);
                                BSTmp(105) := DataInL(15);
                                BSTmp(104) := DataInR(15);
                                BSTmp(103) := DataInL(14);
                                BSTmp(102) := DataInR(14);
                                BSTmp(101)