idt70t3399.vhd

vhdl cod for ram.For sp3e

        w_127 : VitalWireDelay (ADSNegR_ipd   , ADSNegR   , tipd_ADSNegR);
        w_128 : VitalWireDelay (CNTENNegR_ipd , CNTENNegR , tipd_CNTENNegR);
        w_129 : VitalWireDelay (REPEATNegR_ipd, REPEATNegR, tipd_REPEATNegR);
        w_132 : VitalWireDelay (UBNegR_ipd   , UBNegR   , tipd_UBNegR);
        w_133 : VitalWireDelay (LBNegR_ipd   , LBNegR   , tipd_LBNegR);
        w_134 : VitalWireDelay (ZZR_ipd       , ZZR       , tipd_ZZR    );
        w_135 : VitalWireDelay (TMS_ipd       , TMS       , tipd_TMS    );
        w_136 : VitalWireDelay (TRSTNeg_ipd   , TRSTNeg   , tipd_TRSTNeg);
        w_137 : VitalWireDelay (TCK_ipd       , TCK       , tipd_TCK    );
        w_138 : VitalWireDelay (TDI_ipd       , TDI       , tipd_TDI    );
        w_139 : VitalWireDelay (OENegR_ipd    , OENegR    , tipd_OENegR );
        w_140 : VitalWireDelay (PLNegL_ipd    , PLNegL    , tipd_PLNegL );
        w_141 : VitalWireDelay (PLNegR_ipd    , PLNegR    , tipd_PLNegR );

    END BLOCK;

    ---------------------------------------------------------------------------
    -- Main Behavior Block
    ---------------------------------------------------------------------------
    Behavior: BLOCK
    PORT (
        AddressL          : IN    std_logic_vector(HiAddrBit downto 0);
        DataInL           : IN    std_logic_vector(17 downto 0);
        DataOutL          : OUT   std_logic_vector(17 downto 0);
        RWL               : IN    std_logic;
        CEL               : IN    std_logic_vector(1 downto 0);
        OEL               : IN    std_logic;
        ClockL            : IN    std_logic;
        PLNegL            : IN    std_logic;
        ADSNegL           : IN    std_logic;
        CNTENNegL         : IN    std_logic;
        REPEATNegL        : IN    std_logic;
        BENegL            : IN    std_logic_vector(1 downto 0);
        ZZL               : IN    std_logic;
        INTNegL           : OUT   std_logic;
        COLNegL           : OUT   std_logic;

        AddressR          : IN    std_logic_vector(HiAddrBit downto 0);
        DataInR           : IN    std_logic_vector(17 downto 0);
        DataOutR          : OUT   std_logic_vector(17 downto 0);
        RWR               : IN    std_logic;
        CER               : IN    std_logic_vector(1 downto 0);
        OER               : IN    std_logic;
        ClockR            : IN    std_logic;
        PLNegR            : IN    std_logic;
        ADSNegR           : IN    std_logic;
        CNTENNegR         : IN    std_logic;
        REPEATNegR        : IN    std_logic;
        BENegR            : IN    std_logic_vector(1 downto 0);
        ZZR               : IN    std_logic;
        INTNegR           : OUT   std_logic;
        COLNegR           : OUT   std_logic;

        TDI               : IN    std_logic;
        TCK               : IN    std_logic;
        TMS               : IN    std_logic;
        TRSTNeg           : IN    std_logic;
        TDO               : OUT   std_logic
    );
    PORT MAP (
        AddressL(0 )    => A0L_ipd   ,
        AddressL(1 )    => A1L_ipd   ,
        AddressL(2 )    => A2L_ipd   ,
        AddressL(3 )    => A3L_ipd   ,
        AddressL(4 )    => A4L_ipd   ,
        AddressL(5 )    => A5L_ipd   ,
        AddressL(6 )    => A6L_ipd   ,
        AddressL(7 )    => A7L_ipd   ,
        AddressL(8 )    => A8L_ipd   ,
        AddressL(9 )    => A9L_ipd   ,
        AddressL(10)    => A10L_ipd ,
        AddressL(11)    => A11L_ipd ,
        AddressL(12)    => A12L_ipd ,
        AddressL(13)    => A13L_ipd ,
        AddressL(14)    => A14L_ipd ,
        AddressL(15)    => A15L_ipd ,
        AddressL(16)    => A16L_ipd ,

        DataInL(0 )     => IO0L_ipd    ,
        DataInL(1 )     => IO1L_ipd    ,
        DataInL(2 )     => IO2L_ipd    ,
        DataInL(3 )     => IO3L_ipd    ,
        DataInL(4 )     => IO4L_ipd    ,
        DataInL(5 )     => IO5L_ipd    ,
        DataInL(6 )     => IO6L_ipd    ,
        DataInL(7 )     => IO7L_ipd    ,
        DataInL(8 )     => IO8L_ipd    ,
        DataInL(9 )     => IO9L_ipd    ,
        DataInL(10)     => IO10L_ipd   ,
        DataInL(11)     => IO11L_ipd   ,
        DataInL(12)     => IO12L_ipd   ,
        DataInL(13)     => IO13L_ipd   ,
        DataInL(14)     => IO14L_ipd   ,
        DataInL(15)     => IO15L_ipd   ,
        DataInL(16)     => IO16L_ipd   ,
        DataInL(17)     => IO17L_ipd   ,

        DataOutL(0 )    => IO0L    ,
        DataOutL(1 )    => IO1L    ,
        DataOutL(2 )    => IO2L    ,
        DataOutL(3 )    => IO3L    ,
        DataOutL(4 )    => IO4L    ,
        DataOutL(5 )    => IO5L    ,
        DataOutL(6 )    => IO6L    ,
        DataOutL(7 )    => IO7L    ,
        DataOutL(8 )    => IO8L    ,
        DataOutL(9 )    => IO9L    ,
        DataOutL(10)    => IO10L   ,
        DataOutL(11)    => IO11L   ,
        DataOutL(12)    => IO12L   ,
        DataOutL(13)    => IO13L   ,
        DataOutL(14)    => IO14L   ,
        DataOutL(15)    => IO15L   ,
        DataOutL(16)    => IO16L   ,
        DataOutL(17)    => IO17L   ,

        RWL             => RWL_ipd       ,
        CEL(0)          => CE0NegL_ipd   ,
        CEL(1)          => CE1L_ipd      ,
        OEL             => OENegL_ipd   ,
        ClockL          => CLKL_ipd      ,
        CNTENNegL       => CNTENNegL_ipd ,
        PLNegL          => PLNegL_ipd    ,
        ADSNegL         => ADSNegL_ipd   ,
        REPEATNegL      => REPEATNegL_ipd,
        BENegL(0)       => LBNegL_ipd   ,
        BENegL(1)       => UBNegL_ipd   ,
        ZZL             => ZZL_ipd       ,
        INTNegL         => INTNegL       ,
        COLNegL         => COLNegL       ,

        AddressR(0 )    => A0R_ipd   ,
        AddressR(1 )    => A1R_ipd   ,
        AddressR(2 )    => A2R_ipd   ,
        AddressR(3 )    => A3R_ipd   ,
        AddressR(4 )    => A4R_ipd   ,
        AddressR(5 )    => A5R_ipd   ,
        AddressR(6 )    => A6R_ipd   ,
        AddressR(7 )    => A7R_ipd   ,
        AddressR(8 )    => A8R_ipd   ,
        AddressR(9 )    => A9R_ipd   ,
        AddressR(10)    => A10R_ipd ,
        AddressR(11)    => A11R_ipd ,
        AddressR(12)    => A12R_ipd ,
        AddressR(13)    => A13R_ipd ,
        AddressR(14)    => A14R_ipd ,
        AddressR(15)    => A15R_ipd ,
        AddressR(16)    => A16R_ipd ,

        DataInR(0 )     => IO0R_ipd    ,
        DataInR(1 )     => IO1R_ipd    ,
        DataInR(2 )     => IO2R_ipd    ,
        DataInR(3 )     => IO3R_ipd    ,
        DataInR(4 )     => IO4R_ipd    ,
        DataInR(5 )     => IO5R_ipd    ,
        DataInR(6 )     => IO6R_ipd    ,
        DataInR(7 )     => IO7R_ipd    ,
        DataInR(8 )     => IO8R_ipd    ,
        DataInR(9 )     => IO9R_ipd    ,
        DataInR(10)     => IO10R_ipd   ,
        DataInR(11)     => IO11R_ipd   ,
        DataInR(12)     => IO12R_ipd   ,
        DataInR(13)     => IO13R_ipd   ,
        DataInR(14)     => IO14R_ipd   ,
        DataInR(15)     => IO15R_ipd   ,
        DataInR(16)     => IO16R_ipd   ,
        DataInR(17)     => IO17R_ipd   ,

        DataOutR(0 )    => IO0R    ,
        DataOutR(1 )    => IO1R    ,
        DataOutR(2 )    => IO2R    ,
        DataOutR(3 )    => IO3R    ,
        DataOutR(4 )    => IO4R    ,
        DataOutR(5 )    => IO5R    ,
        DataOutR(6 )    => IO6R    ,
        DataOutR(7 )    => IO7R    ,
        DataOutR(8 )    => IO8R    ,
        DataOutR(9 )    => IO9R    ,
        DataOutR(10)    => IO10R   ,
        DataOutR(11)    => IO11R   ,
        DataOutR(12)    => IO12R   ,
        DataOutR(13)    => IO13R   ,
        DataOutR(14)    => IO14R   ,
        DataOutR(15)    => IO15R   ,
        DataOutR(16)    => IO16R   ,
        DataOutR(17)    => IO17R   ,

        RWR             => RWR_ipd       ,
        CER(0)          => CE0NegR_ipd   ,
        CER(1)          => CE1R_ipd      ,
        OER             => OENegR_ipd   ,
        ClockR          => CLKR_ipd      ,
        CNTENNegR       => CNTENNegR_ipd ,
        PLNegR          => PLNegR_ipd    ,
        ADSNegR         => ADSNegR_ipd   ,
        REPEATNegR      => REPEATNegR_ipd,
        BENegR(0)       => LBNegR_ipd   ,
        BENegR(1)       => UBNegR_ipd   ,
        ZZR             => ZZR_ipd       ,
        INTNegR         => INTNegR       ,
        COLNegR         => COLNegR       ,

        TDI             => TDI_ipd     ,
        TCK             => TCK_ipd     ,
        TMS             => TMS_ipd     ,
        TRSTNeg         => TRSTNeg_ipd ,
        TDO             => TDO
    );

    SIGNAL DOL_zd  : std_logic_vector(17 downto 0);
    SIGNAL DOR_zd  : std_logic_vector(17 downto 0);
    SIGNAL Viol    : X01 := '0';

    TYPE Instruction IS (idcode,
                         extest,
                         bypass,
                         highz,
                         sample_preload,
                         clamp,
                         reserved
                        );

    SIGNAL Instruct  : Instruction;
    SIGNAL BSReg     : std_logic_vector(111 downto 0) := (OTHERS => '1');

BEGIN
-------------------------------------------------------------------------------
-- Timing Check and JTAG
-------------------------------------------------------------------------------
    TimingCheckP: PROCESS(AddressL, DataInL, RWL, CEL, OEL, ClockL, PLNegL,
                          ADSNegL, CNTENNegL, REPEATNegL, BENegL,
                          AddressR, DataInR, RWR, CER, OER, ClockR, PLNegR,
                          ADSNegR, CNTENNegR, REPEATNegR, BENegR,
                          TDI, TCK, TMS, TRSTNeg)

        TYPE tap_state_type IS (Test_Logic_Reset,
                                Run_Test_Idle,
                                Select_DR_Scan,
                                Capture_DR,
                                Shift_DR,
                                Exit1_DR,
                                Pause_DR,
                                Exit2_DR,
                                Update_DR,
                                Select_IR_Scan,
                                Capture_IR,
                                Shift_IR,
                                Exit1_IR,
                                Pause_IR,
                                Exit2_IR,
                                Update_IR
                                );

        VARIABLE TAP_state   : tap_state_type;

        VARIABLE BYReg       : std_logic := '0';
        VARIABLE MSReg       : std_logic_vector(1 downto 0) := "00";
        VARIABLE IReg        : std_logic_vector(3 downto 0);
        VARIABLE MRReg       : std_logic_vector(25 downto 0)
                                    := (others => '0');
        VARIABLE IDReg       : std_logic_vector(31 downto 0);
        VARIABLE BYTmp       : std_logic;
        VARIABLE MSTmp       : std_logic_vector(1 downto 0);
        VARIABLE ITmp        : std_logic_vector(3 downto 0);
        VARIABLE MRTmp       : std_logic_vector(25 downto 0);
        VARIABLE IDTmp       : std_logic_vector(31 downto 0);
        VARIABLE BSTmp       : std_logic_vector(111 downto 0)
                                    := (others => '1');
        VARIABLE TDOTmp      : std_logic;

        VARIABLE Shift       : BOOLEAN := false;
        VARIABLE UpdateIR    : BOOLEAN := false;
        VARIABLE UpdateDR    : BOOLEAN := false;