cy7c106.vhd

vhdl cod for ram.For sp3e

--------------------------------------------------------------------------------
--  File Name: cy7c106.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1998-2008 Free Model Foundry; http://www.FreeModelFoundry.com
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--  MODIFICATION HISTORY:
-- 
--  version: |  author:  | mod date: | changes made:
--    V1.0     R. Steele   98 SEP 12   Initial release (of sram256k4)
--    V1.1     R. Munden   99 JAN 07   Modified sram256k4 to make cy7c106
--    V1.2     R. Munden   02 APR 01   Corrected timing check
--    V1.3     R. Munden   08 MAY 23   Removed extra tipd generic
-- 
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
-- 
--  Library:     MEM
--  Technology:  not ECL
--  Part:        SRAM256K4
-- 
--  Description: 256K X 4 SRAM
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;
                USE FMF.conversions.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY cy7c106 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_OENeg          : VitalDelayType01 := VitalZeroDelay01;
        tipd_WENeg          : VitalDelayType01 := VitalZeroDelay01;
        tipd_CENeg          : VitalDelayType01 := VitalZeroDelay01;
        tipd_D0             : VitalDelayType01 := VitalZeroDelay01;
        tipd_D1             : VitalDelayType01 := VitalZeroDelay01;
        tipd_D2             : VitalDelayType01 := VitalZeroDelay01;
        tipd_D3             : VitalDelayType01 := VitalZeroDelay01;
        tipd_A0             : VitalDelayType01 := VitalZeroDelay01;
        tipd_A1             : VitalDelayType01 := VitalZeroDelay01;
        tipd_A2             : VitalDelayType01 := VitalZeroDelay01;
        tipd_A3             : VitalDelayType01 := VitalZeroDelay01;
        tipd_A4             : VitalDelayType01 := VitalZeroDelay01;
        tipd_A5             : VitalDelayType01 := VitalZeroDelay01;
        tipd_A6             : VitalDelayType01 := VitalZeroDelay01;
        tipd_A7             : VitalDelayType01 := VitalZeroDelay01;
        tipd_A8             : VitalDelayType01 := VitalZeroDelay01;
        tipd_A9             : VitalDelayType01 := VitalZeroDelay01;
        tipd_A10            : VitalDelayType01 := VitalZeroDelay01;
        tipd_A11            : VitalDelayType01 := VitalZeroDelay01;
        tipd_A12            : VitalDelayType01 := VitalZeroDelay01;
        tipd_A13            : VitalDelayType01 := VitalZeroDelay01;
        tipd_A14            : VitalDelayType01 := VitalZeroDelay01;
        tipd_A15            : VitalDelayType01 := VitalZeroDelay01;
        tipd_A16            : VitalDelayType01 := VitalZeroDelay01;
        tipd_A17            : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_OENeg_D0                    : VitalDelayType01Z := UnitDelay01Z;
        tpd_CENeg_D0                    : VitalDelayType01Z := UnitDelay01Z;
        tpd_A0_D0                       : VitalDelayType01  := UnitDelay01;
        -- tpw values: pulse widths
        tpw_WENeg_negedge               : VitalDelayType    := UnitDelay;
        tpw_WENeg_posedge               : VitalDelayType    := UnitDelay;
        -- tsetup values: setup times
        tsetup_D0_WENeg                 : VitalDelayType    := UnitDelay;
        tsetup_A0_WENeg                 : VitalDelayType    := UnitDelay;
        tsetup_D0_CENeg                 : VitalDelayType    := UnitDelay;
        -- thold values: hold times
        thold_D0_WENeg                  : VitalDelayType    := UnitDelay;
        thold_A0_WENeg                  : VitalDelayType    := UnitDelay;
        thold_D0_CENeg                  : VitalDelayType    := UnitDelay;
        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXOn;
        SeverityMode        : SEVERITY_LEVEL := WARNING;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        A0              : IN    std_ulogic := 'U';
        A1              : IN    std_ulogic := 'U';
        A2              : IN    std_ulogic := 'U';
        A3              : IN    std_ulogic := 'U';
        A4              : IN    std_ulogic := 'U';
        A5              : IN    std_ulogic := 'U';
        A6              : IN    std_ulogic := 'U';
        A7              : IN    std_ulogic := 'U';
        A8              : IN    std_ulogic := 'U';
        A9              : IN    std_ulogic := 'U';
        A10             : IN    std_ulogic := 'U';
        A11             : IN    std_ulogic := 'U';
        A12             : IN    std_ulogic := 'U';
        A13             : IN    std_ulogic := 'U';
        A14             : IN    std_ulogic := 'U';
        A15             : IN    std_ulogic := 'U';
        A16             : IN    std_ulogic := 'U';
        A17             : IN    std_ulogic := 'U';

        D0              : INOUT std_ulogic := 'U';
        D1              : INOUT std_ulogic := 'U';
        D2              : INOUT std_ulogic := 'U';
        D3              : INOUT std_ulogic := 'U';

        OENeg           : IN    std_ulogic := 'U';
        WENeg           : IN    std_ulogic := 'U';
        CENeg           : IN    std_ulogic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of cy7c106 : ENTITY IS TRUE;
END cy7c106;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of cy7c106 IS
    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    ----------------------------------------------------------------------------
    -- Note that this style of model departs significantly from the original
    -- intent of the VITAL spec.  The timing checks section does not generate
    -- any 'X' values for output results since the array only stores integer
    -- values.  So, to check for timing errors one will have to monitor the
    -- warning messages closely.  Also, the path delay procedures are included
    -- in their own processes which are generated as a function of data width.
    -- This method together with the behavior block aids in reducing coding
    -- by converting the address bus and data bus to vectors.  Scalars on the
    -- input ports is necessary for backannotation of wire delays.
    ----------------------------------------------------------------------------

    CONSTANT partID         : STRING := "cy7c106";
    CONSTANT MaxData        : NATURAL := 15;
    CONSTANT TotalLOC       : NATURAL := 262143;

    SIGNAL D0_ipd           : std_ulogic := 'X';
    SIGNAL D1_ipd           : std_ulogic := 'X';
    SIGNAL D2_ipd           : std_ulogic := 'X';
    SIGNAL D3_ipd           : std_ulogic := 'X';

    SIGNAL A0_ipd           : std_ulogic := 'X';
    SIGNAL A1_ipd           : std_ulogic := 'X';
    SIGNAL A2_ipd           : std_ulogic := 'X';
    SIGNAL A3_ipd           : std_ulogic := 'X';
    SIGNAL A4_ipd           : std_ulogic := 'X';
    SIGNAL A5_ipd           : std_ulogic := 'X';
    SIGNAL A6_ipd           : std_ulogic := 'X';
    SIGNAL A7_ipd           : std_ulogic := 'X';
    SIGNAL A8_ipd           : std_ulogic := 'X';
    SIGNAL A9_ipd           : std_ulogic := 'X';
    SIGNAL A10_ipd          : std_ulogic := 'X';
    SIGNAL A11_ipd          : std_ulogic := 'X';
    SIGNAL A12_ipd          : std_ulogic := 'X';
    SIGNAL A13_ipd          : std_ulogic := 'X';
    SIGNAL A14_ipd          : std_ulogic := 'X';
    SIGNAL A15_ipd          : std_ulogic := 'X';
    SIGNAL A16_ipd          : std_ulogic := 'X';
    SIGNAL A17_ipd          : std_ulogic := 'X';

    SIGNAL OENeg_ipd        : std_ulogic := 'X';
    SIGNAL WENeg_ipd        : std_ulogic := 'X';
    SIGNAL CENeg_ipd        : std_ulogic := 'X';


BEGIN
    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1: VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg);
        w_2: VitalWireDelay (WENeg_ipd, WENeg, tipd_WENeg);
        w_3: VitalWireDelay (CENeg_ipd, CENeg, tipd_CENeg);
        w_5: VitalWireDelay (D0_ipd, D0, tipd_D0);
        w_6: VitalWireDelay (D1_ipd, D1, tipd_D1);
        w_7: VitalWireDelay (D2_ipd, D2, tipd_D2);
        w_8: VitalWireDelay (D3_ipd, D3, tipd_D3);
        w_13: VitalWireDelay (A0_ipd, A0, tipd_A0);
        w_14: VitalWireDelay (A1_ipd, A1, tipd_A1);
        w_15: VitalWireDelay (A2_ipd, A2, tipd_A2);
        w_16: VitalWireDelay (A3_ipd, A3, tipd_A3);
        w_17: VitalWireDelay (A4_ipd, A4, tipd_A4);
        w_18: VitalWireDelay (A5_ipd, A5, tipd_A5);
        w_19: VitalWireDelay (A6_ipd, A6, tipd_A6);
        w_20: VitalWireDelay (A7_ipd, A7, tipd_A7);
        w_21: VitalWireDelay (A8_ipd, A8, tipd_A8);
        w_22: VitalWireDelay (A9_ipd, A9, tipd_A9);
        w_23: VitalWireDelay (A10_ipd, A10, tipd_A10);
        w_24: VitalWireDelay (A11_ipd, A11, tipd_A11);
        w_25: VitalWireDelay (A12_ipd, A12, tipd_A12);
        w_26: VitalWireDelay (A13_ipd, A13, tipd_A13);
        w_27: VitalWireDelay (A14_ipd, A14, tipd_A14);
        w_28: VitalWireDelay (A15_ipd, A15, tipd_A15);
        w_29: VitalWireDelay (A16_ipd, A16, tipd_A16);
        w_30: VitalWireDelay (A17_ipd, A17, tipd_A17);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Main Behavior Block
    ----------------------------------------------------------------------------
    Behavior: BLOCK

        PORT (
            AddressIn       : IN    std_logic_vector(17 downto 0);
            DataIn          : IN    std_logic_vector(3 downto 0);
            DataOut         : OUT   std_logic_vector(3 downto 0);