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📄 mt48lc4m32b2.vhd

📁 vhdl cod for ram.For sp3e
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            ASSERT (DQM1In = '1')                REPORT InstancePath & partID & BankString                    &": DQM1 must be held high"                    & " during initialization."                SEVERITY SeverityMode;            ASSERT (DQM2In = '1')                REPORT InstancePath & partID & BankString                    &": DQM2 must be held high"                    &" during initialization."                SEVERITY SeverityMode;            ASSERT (DQM3In = '1')                REPORT InstancePath & partID & BankString                    &": DQM3 must be held high"                    & " during initialization."                SEVERITY SeverityMode;            IF (PoweredUp = false) THEN                ASSERT (command = nop)                    REPORT InstancePath & partID & BankString                        &": Only NOPs allowed"                        & " during power up."                    SEVERITY SeverityMode;                DataDrive := "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";            ELSIF (command = pre) AND ((cur_bank = bank) OR                    (AddressIn(10) = '1')) THEN                statebank(bank) <= precharge, idle AFTER tdevice_TRP;            END IF;        WHEN precharge =>            IF cur_bank = bank THEN                -- It is only an error if this bank is selected                ASSERT (command = nop OR command = pre)                    REPORT InstancePath & partID & BankString                            &": Illegal command received"                            & " during precharge."                    SEVERITY SeverityMode;            END IF;        WHEN idle =>            IF (command = nop OR command = bst OR command = pre) OR                (cur_bank /= bank) THEN                null;            ELSIF (command = mrs) THEN                IF (statebank = idle & idle & idle & idle) THEN                    ModeReg := AddressIn;                    statebank <= mode_set & mode_set & mode_set & mode_set;                END IF;            ELSIF (command = ref) THEN                IF (statebank = idle & idle & idle & idle) THEN                    IF (CKEIn = '1') THEN                        statebank(bank) <= auto_refresh, idle  AFTER                            tdevice_TRCAR;                    ELSE                        statebank <= self_refresh & self_refresh                                & self_refresh & self_refresh;                    END IF;                END IF;            ELSIF (command = act) THEN                statebank(bank) <= bank_act;                ras_in(bank)  <= '1', '0' AFTER 70 ns;                rct_in  <= '1', '0' AFTER 1 ns;                rcdt_in(bank) <= '1', '0' AFTER 1 ns;                MemAddr(bank)(19 downto 8) := AddressIn;  -- latch row addr            ELSE                ASSERT false                    REPORT InstancePath & partID & ": Illegal command"                            & " received in idle state."                    SEVERITY SeverityMode;            END IF;        WHEN mode_set =>            statebank <= idle & idle & idle & idle;            ASSERT (ModeReg(7) = '0' AND ModeReg(8) ='0')                REPORT InstancePath & partID & BankString                        &": Illegal operating mode set."                SEVERITY SeverityMode;            ASSERT command = nop                REPORT InstancePath & partID & BankString                        & ": Illegal command received during mode_set."                SEVERITY SeverityMode;            -- read burst length            IF (ModeReg(2 downto 0) = "000") THEN                BurstLen := 1;                Burst_Bits := 0;            ELSIF (ModeReg(2 downto 0) = "001") THEN                BurstLen := 2;                Burst_Bits := 1;            ELSIF (ModeReg(2 downto 0) = "010") THEN                BurstLen := 4;                Burst_Bits := 2;            ELSIF (ModeReg(2 downto 0) = "011") THEN                BurstLen := 8;                Burst_Bits := 3;            ELSIF (ModeReg(2 downto 0) = "111") THEN                BurstLen := 256;                Burst_Bits := 7;            ELSE                ASSERT false                    REPORT InstancePath & partID & BankString                            &": Invalid burst length specified."                    SEVERITY SeverityMode;            END IF;            -- read burst type            IF (ModeReg(3) = '0') THEN                Burst := sequential;            ELSIF (ModeReg(3) = '1') THEN                Burst := interleave;            ELSE                ASSERT false                    REPORT InstancePath & partID & BankString                            &": Invalid burst type specified."                    SEVERITY SeverityMode;            END IF;            -- read CAS latency            IF (ModeReg(6 downto 4) = "001") THEN                CAS_Lat <= 1;            ELSIF (ModeReg(6 downto 4) = "010") THEN                CAS_Lat <= 2;            ELSIF (ModeReg(6 downto 4) = "011") THEN                CAS_Lat <= 3;            ELSE                ASSERT false                REPORT InstancePath & partID & BankString &                    ": CAS Latency set incorrecty "                SEVERITY SeverityMode;            END IF;            -- read write burst mode            IF (ModeReg(9) = '0') THEN                WB := programmed;            ELSIF (ModeReg(9) = '1') THEN                WB := single;            ELSE                ASSERT false                    REPORT InstancePath & partID & BankString &                            ": Invalid burst type specified."                    SEVERITY SeverityMode;            END IF;        WHEN auto_refresh =>            IF (Ref_Cnt < 4096) THEN                Ref_Cnt := Ref_Cnt + 1;            END IF;            ASSERT command = nop                REPORT InstancePath & partID & BankString &                        ": Illegal command received during auto_refresh."                SEVERITY SeverityMode;        WHEN bank_act =>            IF (command = pre) AND ((cur_bank = bank) OR (AddressIn(10) = '1'))                THEN                ASSERT ras_out(bank) = '1'                    REPORT InstancePath & partID & BankString &                            ": precharge command"                            & " does not meet tRAS time."                    SEVERITY SeverityMode;                statebank(bank) <= precharge, idle AFTER tdevice_TRP;            ELSIF (command = nop OR command = bst) OR (cur_bank /= bank) THEN                null;            ELSIF (command = read) THEN                ASSERT rcdt_out(bank) = '0'                    REPORT InstancePath & partID & BankString &                            ": read command received too soon after active."                    SEVERITY SeverityMode;                ASSERT ((AddressIn(10) = '0') OR (AddressIn(10) = '1'))                    REPORT InstancePath & partID & BankString &                            ": AddressIn(10) = X"                            & " during read command. Next state unknown."                    SEVERITY SeverityMode;                MemAddr(bank)(7 downto 0) := (others => '0'); -- clr old addr                BurstIncProc(Bank);                MemAddr(bank)(7 downto Burst_Bits) :=                            AddressIn(7 downto Burst_Bits); --latch col addr                StartAddr(bank) := BurstInc(bank) mod 8;                BaseLoc(bank) := to_nat(MemAddr(bank));                Loc := 4*(BaseLoc(bank) + BurstInc(bank));                generate_out(Bank);                BurstCnt(bank) := 1;                NextStateAuto(Bank,read);            ELSIF (command = writ) THEN                ASSERT rcdt_out(bank) = '0'                    REPORT InstancePath & partID & BankString &                            ": write command"                            & " received too soon after active."                    SEVERITY SeverityMode;                ASSERT ((AddressIn(10) = '0') OR (AddressIn(10) = '1'))                    REPORT InstancePath & partID & BankString &                            ": AddressIn(10) = X"                            & " during write command. Next state unknown."                    SEVERITY SeverityMode;                MemAddr(bank)(7 downto 0) := (others => '0'); -- clr old addr                BurstIncProc(Bank);                MemAddr(bank)(7 downto Burst_Bits) :=                            AddressIn(7 downto Burst_Bits); --latch col addr                StartAddr(bank) := BurstInc(bank) mod 8;                BaseLoc(bank) := to_nat(MemAddr(bank));                Loc := 4*(BaseLoc(bank) + BurstInc(bank));                MemWrite(Bank);                BurstCnt(bank) := 1;                wrt_in <= '1';                NextStateAuto(Bank,write);                written := true;            ELSIF (cur_bank = bank) OR (command = mrs) THEN                ASSERT false                    REPORT InstancePath & partID & BankString &                            ": Illegal command "                            & "received in active state."                    SEVERITY SeverityMode;            END IF;        WHEN write =>            IF (command = bst) THEN                statebank(bank) <= bank_act;                BurstCnt(bank) := 0;            ELSIF (command = read) THEN                IF (bank = cur_bank) THEN                    MemAddr(bank)(7 downto 0):= (others => '0');-- clr old addr                    BurstIncProc(Bank);                    MemAddr(bank)(7 downto Burst_Bits) :=                            AddressIn(7 downto Burst_Bits); --latch col addr                    StartAddr(bank) := BurstInc(bank) mod 8;                    BaseLoc(bank) := to_nat(MemAddr(bank));                    Loc := 4*(BaseLoc(bank) + BurstInc(bank));                    generate_out(Bank);                    BurstCnt(bank) := 1;                    NextStateAuto(Bank,read);                ELSE                    statebank(bank) <= bank_act;                END IF;            ELSIF (command = writ) THEN                IF cur_bank = bank THEN                    MemAddr(bank)(7 downto 0):=(others => '0');-- clr old addr                    BurstIncProc(Bank);                    MemAddr(bank)(7 downto Burst_Bits) :=                            AddressIn(7 downto Burst_Bits); --latch col addr                    StartAddr(bank) := BurstInc(bank) mod 8;                    BaseLoc(bank) := to_nat(MemAddr(bank));                    Loc := 4*(BaseLoc(bank) + BurstInc(bank));                    MemWrite(Bank);                    BurstCnt(bank) := 1;                    wrt_in <= '1';                    IF (AddressIn(10) = '1') THEN                        statebank(bank) <= write_auto_pre;                    END IF;                ELSE                    statebank(bank) <= bank_act;                END IF;            ELSIF (command = pre) AND ((cur_bank = bank) OR                                (AddressIn(10) = '1')) THEN                ASSERT ras_out(bank) = '1'                    REPORT InstancePath & partID & BankString &                            ": precharge command"                            & " does not meet tRAS time."                    SEVERITY SeverityMode;                ASSERT (DQM0_nwv = '1')                    REPORT InstancePath & partID & BankString &                            ": DQM0 should be"                            & " held high, data is lost."                    SEVERITY SeverityMode;                ASSERT (DQM1_nwv = '1')                    REPORT InstancePath & partID & BankString &                            ": DQM1 should be"                            & " held high, data is lost."                    SEVERITY SeverityMode;               ASSERT (DQM2_nwv = '1')                    REPORT InstancePath & partID & BankString &                            ": DQM2 should be"                            & " held high, data is lost."                    SEVERITY SeverityMode;                ASSERT (DQM3_nwv = '1')                    REPORT InstancePath & partID & BankString &                            ": DQM3 should be"                            & " held high, data is lost."                    SEVERITY SeverityMode;                    wrt_in <= '0';                    statebank(bank) <= precharge, idle AFTER tdevice_TRP;            ELSIF (command = nop) OR (cur_bank /= bank) THEN                IF (BurstCnt(bank) = BurstLen OR WB = single) THEN                    statebank(bank) <= bank_act;                    BurstCnt(bank) := 0;                    ras_in(bank) <= '1';                ELSE                    IF (Burst = sequential) THEN                        BurstInc(bank) := (BurstInc(bank) + 1) MOD BurstLen;                    ELSE                        BurstInc(bank) := intab(StartAddr(bank))                                                (BurstCnt(bank));                    END IF;                    Loc := 4*(BaseLoc(bank) + BurstInc(bank));                    MemWrite(Bank);                    BurstCnt(bank) := BurstCnt(bank) + 1;                  

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