at28c010.vhd

vhdl cod for ram.For sp3e

                    IF ((Address = 16#5555#) AND (DataByte = 16#A0#))THEN
                        next_state <= SDPEN_PROT;
                    ELSIF ((Address = 16#5555#) AND (DataByte = 16#80#)) THEN
                        next_state <= SDPDI_1;
                    ELSE
                        next_state <= IDLE;
                    END IF;
                END IF;

            WHEN SDPEN_PROT       =>
                IF rising_edge(write) THEN
                    next_state <= WRT;
                END IF;

           WHEN SDPDI_1      =>
               IF rising_edge(write_tmp) THEN
                   IF ((Address = 16#5555#) AND (DataByte = 16#AA#)) THEN
                       next_state <= SDPDI_2;
                   ELSE
                       next_state <= IDLE;
                   END IF;
               END IF;

           WHEN SDPDI_2      =>
               IF rising_edge(write_tmp) THEN
                   IF ((Address = 16#2AAA#) AND (DataByte = 16#55#)) THEN
                       next_state <= SDPDI_3;
                   ELSE
                        next_state <= IDLE;
                   END IF;
               END IF;

            WHEN SDPDI_3      =>
                IF rising_edge(write_tmp) THEN
                    IF ((Address = 16#5555#) AND (DataByte = 16#20#)) THEN
                        next_state <= SDPDI_EXIT;
                    ELSE
                        next_state <= IDLE;
                    END IF;
                END IF;

            WHEN SDPDI_EXIT      =>
                IF rising_edge(write) THEN
                    next_state <= WRT;
                END IF;

        END CASE;

END PROCESS StateGen;

    ---------------------------------------------------------------------------
    --FSM Output generation and general funcionality
    ---------------------------------------------------------------------------
    Functional : PROCESS(write,read, WDONE, current_state, CENeg_ipd,
                         OENeg_ipd, Address, WENeg_ipd)

        VARIABLE oe          : boolean := FALSE;

        VARIABLE Addr        : NATURAL;
        VARIABLE byte_cnt    : NATURAL;

        VARIABLE read_addr   : NATURAL RANGE 0 TO AddrRANGE;
        VARIABLE write_addr  : NATURAL RANGE 0 TO AddrRANGE;
        VARIABLE data_out    : std_logic_vector(7 downto 0);
        VARIABLE write_addr_vect : std_logic_vector(HiAddrBit downto 0);
        VARIABLE page_addr   : std_logic_vector(HiAddrBit downto 0);
        VARIABLE wpage_bad_addr  : std_logic;
    BEGIN
        -----------------------------------------------------------------------
        -- Functionality Section
        -----------------------------------------------------------------------

        oe := rising_edge(read) OR (read = '1' AND Address'EVENT);

        read_addr   := Address;
        write_addr  := Address;

        CASE current_state IS
            WHEN IDLE          =>
                 IF rising_edge(write) THEN
                    WSTART <= '1', '0' AFTER 1 ns;
                    WPSTART <= '1', '0' AFTER 1 ns;
                    WEN <= '1';
                    RDY <= '1';
                 END IF;

                IF oe THEN
                    --Read Memory array
                    data_out := to_slv(Mem(read_addr),8);
                    DOut_zd <= data_out;
                END IF;

            WHEN WRT       =>
                IF oe THEN
                    data_out(7) := NOT IO_tmp(7);
                    data_out(6) := NOT data_out(6);
                    DOut_zd <= data_out;
                END IF;

                IF rising_edge (write) THEN
                    data_out := IO_tmp;
                    WEN <= '1';
                    WSTART <= '1', '0' AFTER 1 ns;
                    WPSTART <= '1', '0' AFTER 1 ns;
                    IF WPDONE = '1' OR byte_cnt > 128 THEN 
                        WEN <= '0';
                        RDY <= '0';
                    END IF;
                END IF;

                write_addr_vect := to_slv(write_addr,HiAddrBit+1);

                IF falling_edge(write) AND WPDONE = '0' 
                AND byte_cnt = 0 AND WEN = '1'  THEN

                    WRITE_BUFFER(byte_cnt) := to_nat(IO_tmp);
                    Mem(write_addr) := to_nat(IO_tmp);
                    page_addr := write_addr_vect;
                    byte_cnt := byte_cnt + 1;
                ELSIF falling_edge(write) AND WPDONE = '0' 
                AND byte_cnt > 0 AND WEN = '1'
                AND write_addr_vect(HiAddrBit downto 7)
                = page_addr(HiAddrBit downto 7) THEN

                    WRITE_BUFFER(byte_cnt) := to_nat(IO_tmp);
                    Mem(write_addr) := to_nat(IO_tmp);
                    byte_cnt := byte_cnt + 1;
                ELSIF write_addr_vect(HiAddrBit downto 7)
                          /= page_addr(HiAddrBit downto 7) AND byte_cnt > 0 THEN
                    wpage_bad_addr := '1';
                END IF;

                IF WDONE = '1' OR wpage_bad_addr = '1' THEN
                    byte_cnt := 0;
                    WEN <= '0';
                    wpage_bad_addr := '0';
                END IF;

            WHEN SDPEN_ENTRY       =>
                NULL;

            WHEN SDPEN_LOAD       =>
                NULL;

            WHEN SDPEN_PROT       =>
                PROT := TRUE;

            WHEN SDPDI_1      =>
                NULL;

            WHEN SDPDI_2      =>
                NULL;

            WHEN SDPDI_3      =>
                NULL;

            WHEN SDPDI_EXIT      =>
               PROT := FALSE;

        END CASE;

        --Output Disable Control
        IF (CENeg_ipd = '1' OR OENeg_ipd = '1') THEN
            DOut_zd <= (OTHERS => 'Z');
        END IF;

END PROCESS Functional;

    ---------------------------------------------------------------------------
    ---- File Read Section - Preload Control
    ---------------------------------------------------------------------------
    MemPreload : PROCESS

        -- text file input variables
        FILE mem_file         : text  is  mem_file_name;
        VARIABLE ind         : NATURAL := 0;
        VARIABLE buf         : line;

    BEGIN
    ---------------------------------------------------------------------------
    --s25320a memory preload file format  -----------------------------------
    ---------------------------------------------------------------------------
    --   /       - comment
    --   @aaaaaa - <aaa> stands for address
    --   dd      - <dd> is byte to be written at Mem(aaa++)
    --             (aaa is incremented at every load)
    --   only first 1-7 columns are loaded. NO empty lines !!!!!!!!!!!!!!!!
    ---------------------------------------------------------------------------

         -- memory preload
        IF (mem_file_name /= "none" AND UserPreload) THEN
            ind := 0;
            Mem := (OTHERS => MaxData);
            WHILE (not ENDFILE (mem_file)) LOOP
                READLINE (mem_file, buf);
                IF buf(1) = '/' THEN
                    NEXT;
                ELSIF buf(1) = '@' THEN
                    ind := h(buf(2 to 6)); --address
                    IF ind > AddrRANGE THEN
                        ASSERT false
                            REPORT "Given preload address is out of" &
                                   "memory address range"
                            SEVERITY warning;
                    END IF;
                ELSE
                    IF ind <= AddrRANGE THEN
                        Mem(ind) := h(buf(1 to 2));
                    END IF;
                    IF ind < AddrRANGE THEN
                        ind := ind + 1;
                    END IF;
                END IF;
            END LOOP;
        END IF;

        WAIT;
    END PROCESS MemPreload;

    DOutPassThrough : PROCESS(DOut_zd)
        VARIABLE ValidData         : std_logic_vector(7 downto 0);
        VARIABLE CEDQ_t            : TIME;
        VARIABLE OEDQ_t            : TIME;
        VARIABLE ADDRDQ_t          : TIME;

    BEGIN
       IF DOut_zd(0) /= 'Z' THEN
           OPENLATCH := TRUE;
           CEDQ_t    := -CENeg'LAST_EVENT + tpd_CENeg_IO0(trz0);
           OEDQ_t    := -OENeg'LAST_EVENT + tpd_OENeg_IO0(trz0);
           ADDRDQ_t  := -A'LAST_EVENT     + tpd_A0_IO0(tr01);
           FROMOE    := (OEDQ_t >= CEDQ_t) AND (OEDQ_t > 0 ns);
           FROMCE    := (CEDQ_t > OEDQ_t)  AND (CEDQ_t > 0 ns);
           ValidData := "XXXXXXXX";
           IF ((ADDRDQ_t > 0 ns) AND
           (((ADDRDQ_t > CEDQ_t) AND FROMCE) OR
            ((ADDRDQ_t > OEDQ_t) AND FROMOE))) THEN
               IOOut_Pass <= ValidData,
                            DOut_zd AFTER ADDRDQ_t;
           ELSE
               IOOut_Pass <= DOut_zd;
           END IF;
       ELSE
           CEDQ_t := -CENeg'LAST_EVENT + tpd_CENeg_IO0(tr0z);
           OEDQ_t := -OENeg'LAST_EVENT + tpd_OENeg_IO0(tr0z);
           FROMOE := (OEDQ_t <= CEDQ_t) AND (OEDQ_t > 0 ns);
           FROMCE := (CEDQ_t < OEDQ_t)  AND (CEDQ_t > 0 ns);
           IOOut_Pass <= DOut_zd;
           OPENLATCH := FALSE;
       END IF;
   END PROCESS DOutPassThrough;

    ---------------------------------------------------------------------------
    -- Path Delay Section for IOOut signal
    ---------------------------------------------------------------------------
    IO_Out_PathDelay_Gen : FOR i IN IOOut_Pass'RANGE GENERATE
        PROCESS(IOOut_Pass(i))
        VARIABLE IO0_GlitchData     : VitalGlitchDataType;

    BEGIN
        VitalPathDelay01Z (
            OutSignal       => IOOut(i),
            OutSignalName   => "IOOut",
            OutTemp         => IOOut_Pass(i),
            GlitchData      => IO0_GlitchData,
            Mode            => VitalTransport,
            Paths           => (
                0 => (InputChangeTime => CENeg'LAST_EVENT,
                      PathDelay       => tpd_CENeg_IO0,
                      PathCondition   => (NOT OPENLATCH AND NOT FROMOE)
                                          OR (OPENLATCH AND FROMCE)),
                1 => (InputChangeTime => OENeg'LAST_EVENT,
                      PathDelay       => tpd_OENeg_IO0,
                      PathCondition   => (NOT OPENLATCH AND NOT FROMOE)
                                          OR (OPENLATCH AND FROMOE)),
                2 => (InputChangeTime => A'LAST_EVENT,
                      PathDelay       => VitalExtendToFillDelay(tpd_A0_IO0),
                      PathCondition   => (NOT FROMOE) AND (NOT FROMCE))
            )
        );

           END PROCESS;
    END GENERATE IO_Out_PathDelay_Gen;

    END BLOCK behavior;
END vhdl_behavioral;